From: Rhyland Klein <rklein@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Mike Turquette <mturquette@baylibre.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, Rhyland Klein <rklein@nvidia.com>
Subject: [Patch V2 4/9] clk: tegra: Fix the misnaming of nvenc from msenc
Date: Thu, 14 Jan 2016 14:24:33 -0500 [thread overview]
Message-ID: <1452799478-14791-5-git-send-email-rklein@nvidia.com> (raw)
In-Reply-To: <1452799478-14791-1-git-send-email-rklein@nvidia.com>
When adding the nvenc clock, it was partially named msenc in
the code. Since the msenc clk isn't present in T210 where the nvenc
clk is, its misleading to see it present. Therefore, properly
rename it.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
---
drivers/clk/tegra/clk-tegra-periph.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 105405ca85ab..1860df1862dd 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -773,7 +773,7 @@ static struct tegra_periph_init_data periph_clks[] = {
XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
- MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
+ MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
--
1.9.1
next prev parent reply other threads:[~2016-01-14 19:25 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-14 19:24 [Patch V2 0/9] Tegra CLK Fixes Rhyland Klein
2016-01-14 19:24 ` [Patch V2 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein
2016-01-25 12:30 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein
2016-01-25 12:34 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein
2016-01-25 12:36 ` Thierry Reding
2016-01-14 19:24 ` Rhyland Klein [this message]
2016-01-25 12:36 ` [Patch V2 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Thierry Reding
2016-01-14 19:24 ` [Patch V2 5/9] clk: tegra: pll: Fix potential sleeping-while-atomic Rhyland Klein
2016-01-25 12:40 ` Thierry Reding
2016-01-25 12:41 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein
2016-01-25 12:47 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein
2016-01-25 12:45 ` Thierry Reding
2016-01-25 12:46 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 8/9] clk: tegra: pll: Fix typos around clearing plle bits during enable Rhyland Klein
2016-01-25 12:47 ` Thierry Reding
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