[PATCH 00/15] dmaengine: dw: various fixes and cleanups

[PATCH 00/15] dmaengine: dw: various fixes and cleanups

[Mans Rullgard]

This patch series contains a number of mostly minor fixes and cleanups
for the DW DMA driver.  A couple of them affect the DT binding so these
may need to be updated to maintain compatibility.  The rest should be
relatively straight-forward.

Andy's branch had two additional patches which I have ommitted here since
one, "dmaengine: dw: clear soft LLP flag in case of error", doesn't look
correct and the other, "dmaengine: dw: split dwc_dostart() helper to two",
depends on the first.

Andy Shevchenko (11):
  dmaengine: dw: rename masters to reflect actual topology
  dmaengine: dw: substitute dma_read_byaddr by dma_readl_native
  dmaengine: dw: revisit data_width property
  dmaengine: dw: define counter variables as unsigned int
  dmaengine: dw: keep entire platform data in struct dw_dma
  dmaengine: dw: pass platform data via struct dw_dma_chip
  dmaengine: dw: platform: use field-by-field initialization
  dmaengine: dw: move dwc->paused to dwc->flags
  dmaengine: dw: move dwc->initialized to dwc->flags
  dmaengine: dw: move residue to a descriptor
  dmaengine: dw: set cdesc to NULL when free cyclic transfers

Mans Rullgard (4):
  dmaengine: dw: fix byte order of hw descriptor fields
  dmaengine: dw: clear LLP_[SD]_EN bits in last descriptor of a chain
  dmaengine: dw: set src and dst master select according to xfer
    direction
  dmaengine: dw: set LMS field in descriptors

 Documentation/devicetree/bindings/dma/snps-dma.txt |   9 +-
 arch/arc/boot/dts/abilis_tb10x.dtsi                |   2 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |   4 +-
 arch/avr32/mach-at32ap/at32ap700x.c                |  16 +-
 drivers/ata/sata_dwc_460ex.c                       |   6 +-
 drivers/dma/dw/core.c                              | 295 ++++++++++-----------
 drivers/dma/dw/pci.c                               |   3 +-
 drivers/dma/dw/platform.c                          |  38 ++-
 drivers/dma/dw/regs.h                              |  55 ++--
 drivers/spi/spi-pxa2xx-pci.c                       |   8 +-
 drivers/tty/serial/8250/8250_pci.c                 |   8 +-
 include/linux/dma/dw.h                             |  14 +-
 include/linux/platform_data/dma-dw.h               |  15 +-
 sound/soc/intel/common/sst-firmware.c              |   2 +-
 14 files changed, 241 insertions(+), 234 deletions(-)

-- 
2.7.0

[PATCH 01/15] dmaengine: dw: fix byte order of hw descriptor fields

[Mans Rullgard]

If the DMA controller uses a different byte order than the host CPU,
the hardware linked list descriptor fields need to be byte-swapped.

This patch makes the driver write these fields using the same byte
order it uses for mmio accesses to the DMA engine.  I do not know
if this is guaranteed to always be correct.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 105 ++++++++++++++++++++++++--------------------------
 drivers/dma/dw/regs.h |  32 +++++++++++----
 2 files changed, 76 insertions(+), 61 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index e893318560db..cc7c1acc8188 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -210,12 +210,12 @@ static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 	 * Software emulation of LLP mode relies on interrupts to continue
 	 * multi block transfer.
 	 */
-	ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
+	ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN;
 
-	channel_writel(dwc, SAR, desc->lli.sar);
-	channel_writel(dwc, DAR, desc->lli.dar);
+	channel_writel(dwc, SAR, lli_read(desc, sar));
+	channel_writel(dwc, DAR, lli_read(desc, dar));
 	channel_writel(dwc, CTL_LO, ctllo);
-	channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
+	channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi));
 	channel_set_bit(dw, CH_EN, dwc->mask);
 
 	/* Move pointer to next descriptor */
@@ -433,7 +433,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 		}
 
 		/* Check first descriptors llp */
-		if (desc->lli.llp == llp) {
+		if (lli_read(desc, llp) == llp) {
 			/* This one is currently in progress */
 			dwc->residue -= dwc_get_sent(dwc);
 			spin_unlock_irqrestore(&dwc->lock, flags);
@@ -442,7 +442,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 
 		dwc->residue -= desc->len;
 		list_for_each_entry(child, &desc->tx_list, desc_node) {
-			if (child->lli.llp == llp) {
+			if (lli_read(child, llp) == llp) {
 				/* Currently in progress */
 				dwc->residue -= dwc_get_sent(dwc);
 				spin_unlock_irqrestore(&dwc->lock, flags);
@@ -744,25 +744,24 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 		if (!desc)
 			goto err_desc_get;
 
-		desc->lli.sar = src + offset;
-		desc->lli.dar = dest + offset;
-		desc->lli.ctllo = ctllo;
-		desc->lli.ctlhi = xfer_count;
+		lli_write(desc, sar, src + offset);
+		lli_write(desc, dar, dest + offset);
+		lli_write(desc, ctllo, ctllo);
+		lli_write(desc, ctlhi, xfer_count);
 		desc->len = xfer_count << src_width;
 
 		if (!first) {
 			first = desc;
 		} else {
-			prev->lli.llp = desc->txd.phys;
-			list_add_tail(&desc->desc_node,
-					&first->tx_list);
+			lli_write(prev, llp, desc->txd.phys);
+			list_add_tail(&desc->desc_node, &first->tx_list);
 		}
 		prev = desc;
 	}
 
 	if (flags & DMA_PREP_INTERRUPT)
 		/* Trigger interrupt after last block */
-		prev->lli.ctllo |= DWC_CTLL_INT_EN;
+		lli_set(prev, ctllo, DWC_CTLL_INT_EN);
 
 	prev->lli.llp = 0;
 	first->txd.flags = flags;
@@ -832,9 +831,9 @@ slave_sg_todev_fill_desc:
 			if (!desc)
 				goto err_desc_get;
 
-			desc->lli.sar = mem;
-			desc->lli.dar = reg;
-			desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
+			lli_write(desc, sar, mem);
+			lli_write(desc, dar, reg);
+			lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
 			if ((len >> mem_width) > dwc->block_size) {
 				dlen = dwc->block_size << mem_width;
 				mem += dlen;
@@ -844,15 +843,14 @@ slave_sg_todev_fill_desc:
 				len = 0;
 			}
 
-			desc->lli.ctlhi = dlen >> mem_width;
+			lli_write(desc, ctlhi, dlen >> mem_width);
 			desc->len = dlen;
 
 			if (!first) {
 				first = desc;
 			} else {
-				prev->lli.llp = desc->txd.phys;
-				list_add_tail(&desc->desc_node,
-						&first->tx_list);
+				lli_write(prev, llp, desc->txd.phys);
+				list_add_tail(&desc->desc_node, &first->tx_list);
 			}
 			prev = desc;
 			total_len += dlen;
@@ -889,9 +887,9 @@ slave_sg_fromdev_fill_desc:
 			if (!desc)
 				goto err_desc_get;
 
-			desc->lli.sar = reg;
-			desc->lli.dar = mem;
-			desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
+			lli_write(desc, sar, reg);
+			lli_write(desc, dar, mem);
+			lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
 			if ((len >> reg_width) > dwc->block_size) {
 				dlen = dwc->block_size << reg_width;
 				mem += dlen;
@@ -900,15 +898,14 @@ slave_sg_fromdev_fill_desc:
 				dlen = len;
 				len = 0;
 			}
-			desc->lli.ctlhi = dlen >> reg_width;
+			lli_write(desc, ctlhi, dlen >> reg_width);
 			desc->len = dlen;
 
 			if (!first) {
 				first = desc;
 			} else {
-				prev->lli.llp = desc->txd.phys;
-				list_add_tail(&desc->desc_node,
-						&first->tx_list);
+				lli_write(prev, llp, desc->txd.phys);
+				list_add_tail(&desc->desc_node, &first->tx_list);
 			}
 			prev = desc;
 			total_len += dlen;
@@ -923,7 +920,7 @@ slave_sg_fromdev_fill_desc:
 
 	if (flags & DMA_PREP_INTERRUPT)
 		/* Trigger interrupt after last block */
-		prev->lli.ctllo |= DWC_CTLL_INT_EN;
+		lli_set(prev, ctllo, DWC_CTLL_INT_EN);
 
 	prev->lli.llp = 0;
 	first->total_len = total_len;
@@ -1388,50 +1385,50 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
 
 		switch (direction) {
 		case DMA_MEM_TO_DEV:
-			desc->lli.dar = sconfig->dst_addr;
-			desc->lli.sar = buf_addr + (period_len * i);
-			desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
-					| DWC_CTLL_DST_WIDTH(reg_width)
-					| DWC_CTLL_SRC_WIDTH(reg_width)
-					| DWC_CTLL_DST_FIX
-					| DWC_CTLL_SRC_INC
-					| DWC_CTLL_INT_EN);
+			lli_write(desc, dar, sconfig->dst_addr);
+			lli_write(desc, sar, buf_addr + period_len * i);
+			lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan)
+				| DWC_CTLL_DST_WIDTH(reg_width)
+				| DWC_CTLL_SRC_WIDTH(reg_width)
+				| DWC_CTLL_DST_FIX
+				| DWC_CTLL_SRC_INC
+				| DWC_CTLL_INT_EN));
 
-			desc->lli.ctllo |= sconfig->device_fc ?
-				DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
-				DWC_CTLL_FC(DW_DMA_FC_D_M2P);
+			lli_set(desc, ctllo, sconfig->device_fc ?
+					DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
+					DWC_CTLL_FC(DW_DMA_FC_D_M2P));
 
 			break;
 		case DMA_DEV_TO_MEM:
-			desc->lli.dar = buf_addr + (period_len * i);
-			desc->lli.sar = sconfig->src_addr;
-			desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
-					| DWC_CTLL_SRC_WIDTH(reg_width)
-					| DWC_CTLL_DST_WIDTH(reg_width)
-					| DWC_CTLL_DST_INC
-					| DWC_CTLL_SRC_FIX
-					| DWC_CTLL_INT_EN);
+			lli_write(desc, dar, buf_addr + period_len * i);
+			lli_write(desc, sar, sconfig->src_addr);
+			lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan)
+				| DWC_CTLL_SRC_WIDTH(reg_width)
+				| DWC_CTLL_DST_WIDTH(reg_width)
+				| DWC_CTLL_DST_INC
+				| DWC_CTLL_SRC_FIX
+				| DWC_CTLL_INT_EN));
 
-			desc->lli.ctllo |= sconfig->device_fc ?
-				DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
-				DWC_CTLL_FC(DW_DMA_FC_D_P2M);
+			lli_set(desc, ctllo, sconfig->device_fc ?
+					DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
+					DWC_CTLL_FC(DW_DMA_FC_D_P2M));
 
 			break;
 		default:
 			break;
 		}
 
-		desc->lli.ctlhi = (period_len >> reg_width);
+		lli_write(desc, ctlhi, period_len >> reg_width);
 		cdesc->desc[i] = desc;
 
 		if (last)
-			last->lli.llp = desc->txd.phys;
+			lli_write(last, llp, desc->txd.phys);
 
 		last = desc;
 	}
 
 	/* Let's make a cyclic list */
-	last->lli.llp = cdesc->desc[0]->txd.phys;
+	lli_write(last, llp, cdesc->desc[0]->txd.phys);
 
 	dev_dbg(chan2dev(&dwc->chan),
 			"cyclic prepared buf %pad len %zu period %zu periods %d\n",
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 241ff2b1402b..afd340958266 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -308,26 +308,44 @@ static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
 	return container_of(ddev, struct dw_dma, dma);
 }
 
+#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
+typedef __be32 __dw32;
+#else
+typedef __le32 __dw32;
+#endif
+
 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
 struct dw_lli {
 	/* values that are not changed by hardware */
-	u32		sar;
-	u32		dar;
-	u32		llp;		/* chain to next lli */
-	u32		ctllo;
+	__dw32		sar;
+	__dw32		dar;
+	__dw32		llp;		/* chain to next lli */
+	__dw32		ctllo;
 	/* values that may get written back: */
-	u32		ctlhi;
+	__dw32		ctlhi;
 	/* sstat and dstat can snapshot peripheral register state.
 	 * silicon config may discard either or both...
 	 */
-	u32		sstat;
-	u32		dstat;
+	__dw32		sstat;
+	__dw32		dstat;
 };
 
 struct dw_desc {
 	/* FIRST values the hardware uses */
 	struct dw_lli			lli;
 
+#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
+#define lli_set(d, reg, v)		((d)->lli.reg |= cpu_to_be32(v))
+#define lli_clear(d, reg, v)		((d)->lli.reg &= ~cpu_to_be32(v))
+#define lli_read(d, reg)		be32_to_cpu((d)->lli.reg)
+#define lli_write(d, reg, v)		((d)->lli.reg = cpu_to_be32(v))
+#else
+#define lli_set(d, reg, v)		((d)->lli.reg |= cpu_to_le32(v))
+#define lli_clear(d, reg, v)		((d)->lli.reg &= ~cpu_to_le32(v))
+#define lli_read(d, reg)		le32_to_cpu((d)->lli.reg)
+#define lli_write(d, reg, v)		((d)->lli.reg = cpu_to_le32(v))
+#endif
+
 	/* THEN values for driver housekeeping */
 	struct list_head		desc_node;
 	struct list_head		tx_list;
-- 
2.7.0

[PATCH 02/15] dmaengine: dw: clear LLP_[SD]_EN bits in last descriptor of a chain

[Mans Rullgard]

The datasheet requires that the LLP_[SD]_EN bits be cleared whenever
LLP.LOC is zero, i.e. in the last descriptor of a multi-block chain.
Make the driver do this.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index cc7c1acc8188..03ec88f1c161 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -764,6 +764,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 		lli_set(prev, ctllo, DWC_CTLL_INT_EN);
 
 	prev->lli.llp = 0;
+	lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 	first->txd.flags = flags;
 	first->total_len = len;
 
@@ -923,6 +924,7 @@ slave_sg_fromdev_fill_desc:
 		lli_set(prev, ctllo, DWC_CTLL_INT_EN);
 
 	prev->lli.llp = 0;
+	lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 	first->total_len = total_len;
 
 	return &first->txd;
-- 
2.7.0

[PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

The source and destination masters are reflecting buses or their layers to
where the different devices can be connected. The patch changes the master
names to reflect which one is related to which independently on the transfer
direction.

The outcome of the change is that the memory data width is now always limited
by a data width of the master which is dedicated to communicate to memory.

The patch will not break anything since all current users have the same data
width for all masters. Though it would be nice to revisit avr32 plaforms to
check what is the actual hardware topology is used there. It seems that it has
one bus and two masters on it as stated by Table 8-2, that's why everything
works independently on the master in use. The purpose of the sequential patch
is to fix the driver for configuration of more that one bus.

The change is done in the assumption that src_master and dst_master are
reflecting a connection to the memory and peripheral correspondently on all
platforms except 460ex.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 Documentation/devicetree/bindings/dma/snps-dma.txt |  4 ++--
 arch/avr32/mach-at32ap/at32ap700x.c                | 16 ++++++++--------
 drivers/ata/sata_dwc_460ex.c                       |  4 ++--
 drivers/dma/dw/core.c                              | 15 +++++++--------
 drivers/dma/dw/platform.c                          | 12 ++++++------
 drivers/dma/dw/regs.h                              |  4 ++--
 drivers/spi/spi-pxa2xx-pci.c                       |  8 ++++----
 drivers/tty/serial/8250/8250_pci.c                 |  8 ++++----
 include/linux/platform_data/dma-dw.h               |  8 ++++----
 9 files changed, 39 insertions(+), 40 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
index c261598164a7..c99c1ffac199 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -47,8 +47,8 @@ The four cells in order are:
 
 1. A phandle pointing to the DMA controller
 2. The DMA request line number
-3. Source master for transfers on allocated channel
-4. Destination master for transfers on allocated channel
+3. Memory master for transfers on allocated channel
+4. Peripheral master for transfers on allocated channel
 
 Example:
 	
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index bf445aa48282..00d6dcc1d9b6 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1365,8 +1365,8 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
 	slave->dma_dev = &dw_dmac0_device.dev;
 	slave->src_id = 0;
 	slave->dst_id = 1;
-	slave->src_master = 1;
-	slave->dst_master = 0;
+	slave->m_master = 1;
+	slave->p_master = 0;
 
 	data->dma_slave = slave;
 	data->dma_filter = at32_mci_dma_filter;
@@ -2061,16 +2061,16 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
 	if (flags & AC97C_CAPTURE) {
 		rx_dws->dma_dev = &dw_dmac0_device.dev;
 		rx_dws->src_id = 3;
-		rx_dws->src_master = 0;
-		rx_dws->dst_master = 1;
+		rx_dws->m_master = 0;
+		rx_dws->p_master = 1;
 	}
 
 	/* Check if DMA slave interface for playback should be configured. */
 	if (flags & AC97C_PLAYBACK) {
 		tx_dws->dma_dev = &dw_dmac0_device.dev;
 		tx_dws->dst_id = 4;
-		tx_dws->src_master = 0;
-		tx_dws->dst_master = 1;
+		tx_dws->m_master = 0;
+		tx_dws->p_master = 1;
 	}
 
 	if (platform_device_add_data(pdev, data,
@@ -2141,8 +2141,8 @@ at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
 
 	dws->dma_dev = &dw_dmac0_device.dev;
 	dws->dst_id = 2;
-	dws->src_master = 0;
-	dws->dst_master = 1;
+	dws->m_master = 0;
+	dws->p_master = 1;
 
 	if (platform_device_add_data(pdev, data,
 				sizeof(struct atmel_abdac_pdata)))
diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
index 902034991517..80bdcabc293f 100644
--- a/drivers/ata/sata_dwc_460ex.c
+++ b/drivers/ata/sata_dwc_460ex.c
@@ -201,8 +201,8 @@ static struct sata_dwc_host_priv host_pvt;
 static struct dw_dma_slave sata_dwc_dma_dws = {
 	.src_id = 0,
 	.dst_id = 0,
-	.src_master = 0,
-	.dst_master = 1,
+	.m_master = 1,
+	.p_master = 0,
 };
 
 /*
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 03ec88f1c161..8d1b87ff2ac6 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -50,8 +50,8 @@
 		 | DWC_CTLL_SRC_MSIZE(_smsize)			\
 		 | DWC_CTLL_LLP_D_EN				\
 		 | DWC_CTLL_LLP_S_EN				\
-		 | DWC_CTLL_DMS(_dwc->dst_master)		\
-		 | DWC_CTLL_SMS(_dwc->src_master));		\
+		 | DWC_CTLL_DMS(_dwc->p_master)			\
+		 | DWC_CTLL_SMS(_dwc->m_master));		\
 	})
 
 /*
@@ -722,8 +722,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 
 	dwc->direction = DMA_MEM_TO_MEM;
 
-	data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
-			   dw->data_width[dwc->dst_master]);
+	data_width = dw->data_width[dwc->m_master];
 
 	src_width = dst_width = min_t(unsigned int, data_width,
 				      dwc_fast_ffs(src | dest | len));
@@ -815,7 +814,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 		ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 			DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 
-		data_width = dw->data_width[dwc->src_master];
+		data_width = dw->data_width[dwc->m_master];
 
 		for_each_sg(sgl, sg, sg_len, i) {
 			struct dw_desc	*desc;
@@ -871,7 +870,7 @@ slave_sg_todev_fill_desc:
 		ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 			DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 
-		data_width = dw->data_width[dwc->dst_master];
+		data_width = dw->data_width[dwc->m_master];
 
 		for_each_sg(sgl, sg, sg_len, i) {
 			struct dw_desc	*desc;
@@ -949,8 +948,8 @@ bool dw_dma_filter(struct dma_chan *chan, void *param)
 	dwc->src_id = dws->src_id;
 	dwc->dst_id = dws->dst_id;
 
-	dwc->src_master = dws->src_master;
-	dwc->dst_master = dws->dst_master;
+	dwc->m_master = dws->m_master;
+	dwc->p_master = dws->p_master;
 
 	return true;
 }
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index 26edbe3a27ac..d3e1abcebd7f 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -42,13 +42,13 @@ static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
 
 	slave.src_id = dma_spec->args[0];
 	slave.dst_id = dma_spec->args[0];
-	slave.src_master = dma_spec->args[1];
-	slave.dst_master = dma_spec->args[2];
+	slave.m_master = dma_spec->args[1];
+	slave.p_master = dma_spec->args[2];
 
 	if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
 		    slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
-		    slave.src_master >= dw->nr_masters ||
-		    slave.dst_master >= dw->nr_masters))
+		    slave.m_master >= dw->nr_masters ||
+		    slave.p_master >= dw->nr_masters))
 		return NULL;
 
 	dma_cap_zero(cap);
@@ -66,8 +66,8 @@ static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
 		.dma_dev = dma_spec->dev,
 		.src_id = dma_spec->slave_id,
 		.dst_id = dma_spec->slave_id,
-		.src_master = 1,
-		.dst_master = 0,
+		.m_master = 1,
+		.p_master = 0,
 	};
 
 	return dw_dma_filter(chan, &slave);
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index afd340958266..0391f8ff6919 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -249,8 +249,8 @@ struct dw_dma_chan {
 	/* custom slave configuration */
 	u8			src_id;
 	u8			dst_id;
-	u8			src_master;
-	u8			dst_master;
+	u8			m_master;
+	u8			p_master;
 
 	/* configuration passed via .device_config */
 	struct dma_slave_config dma_sconfig;
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index d19d7f28aecb..01ccc7448313 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -132,16 +132,16 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
 		struct dw_dma_slave *slave = c->tx_param;
 
 		slave->dma_dev = &dma_dev->dev;
-		slave->src_master = 1;
-		slave->dst_master = 0;
+		slave->m_master = 1;
+		slave->p_master = 0;
 	}
 
 	if (c->rx_param) {
 		struct dw_dma_slave *slave = c->rx_param;
 
 		slave->dma_dev = &dma_dev->dev;
-		slave->src_master = 1;
-		slave->dst_master = 0;
+		slave->m_master = 1;
+		slave->p_master = 0;
 	}
 
 	spi_pdata.dma_filter = lpss_dma_filter;
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 4097f3f65b3b..aa1b5cc7e158 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -1473,13 +1473,13 @@ byt_serial_setup(struct serial_private *priv,
 		return -EINVAL;
 	}
 
-	rx_param->src_master = 1;
-	rx_param->dst_master = 0;
+	rx_param->m_master = 1;
+	rx_param->p_master = 0;
 
 	dma->rxconf.src_maxburst = 16;
 
-	tx_param->src_master = 1;
-	tx_param->dst_master = 0;
+	tx_param->m_master = 1;
+	tx_param->p_master = 0;
 
 	dma->txconf.dst_maxburst = 16;
 
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 03b6095d3b18..b881b978e486 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -21,15 +21,15 @@
  * @dma_dev:	required DMA master device
  * @src_id:	src request line
  * @dst_id:	dst request line
- * @src_master: src master for transfers on allocated channel.
- * @dst_master: dest master for transfers on allocated channel.
+ * @m_master:	memory master for transfers on allocated channel
+ * @p_master:	peripheral master for transfers on allocated channel
  */
 struct dw_dma_slave {
 	struct device		*dma_dev;
 	u8			src_id;
 	u8			dst_id;
-	u8			src_master;
-	u8			dst_master;
+	u8			m_master;
+	u8			p_master;
 };
 
 /**
-- 
2.7.0

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Hans-Christian Noren Egtvedt]

Around Sun 24 Jan 2016 19:21:50 +0000 or thereabout, Mans Rullgard wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> The source and destination masters are reflecting buses or their layers to
> where the different devices can be connected. The patch changes the master
> names to reflect which one is related to which independently on the transfer
> direction.
> 
> The outcome of the change is that the memory data width is now always limited
> by a data width of the master which is dedicated to communicate to memory.
> 
> The patch will not break anything since all current users have the same data
> width for all masters. Though it would be nice to revisit avr32 plaforms to
> check what is the actual hardware topology is used there. It seems that it has
> one bus and two masters on it as stated by Table 8-2, that's why everything
> works independently on the master in use. The purpose of the sequential patch
> is to fix the driver for configuration of more that one bus.

Not entirely sure what you want to have confirmed here. There are multiple
masters and slaves on the HMATRIX internal bus on AVR32, and the DMA
controller supports up to three simultaneous configurations.

Sounds good to support configuration of more than one bus. I thought we
always did support that? Perhaps it was a non-standard avr32 implementation.

> The change is done in the assumption that src_master and dst_master are
> reflecting a connection to the memory and peripheral correspondently on all
> platforms except 460ex.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Mans Rullgard <mans@mansr.com>

For the avr32 related stuff:

Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>

> ---
>  Documentation/devicetree/bindings/dma/snps-dma.txt |  4 ++--
>  arch/avr32/mach-at32ap/at32ap700x.c                | 16 ++++++++--------
>  drivers/ata/sata_dwc_460ex.c                       |  4 ++--
>  drivers/dma/dw/core.c                              | 15 +++++++--------
>  drivers/dma/dw/platform.c                          | 12 ++++++------
>  drivers/dma/dw/regs.h                              |  4 ++--
>  drivers/spi/spi-pxa2xx-pci.c                       |  8 ++++----
>  drivers/tty/serial/8250/8250_pci.c                 |  8 ++++----
>  include/linux/platform_data/dma-dw.h               |  8 ++++----
>  9 files changed, 39 insertions(+), 40 deletions(-)

<snipp diff>

-- 
Best regards, Hans-Christian Egtvedt

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Måns Rullgård]

Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> writes:

> Around Sun 24 Jan 2016 19:21:50 +0000 or thereabout, Mans Rullgard wrote:
>> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> 
>> The source and destination masters are reflecting buses or their layers to
>> where the different devices can be connected. The patch changes the master
>> names to reflect which one is related to which independently on the transfer
>> direction.
>> 
>> The outcome of the change is that the memory data width is now always limited
>> by a data width of the master which is dedicated to communicate to memory.
>> 
>> The patch will not break anything since all current users have the same data
>> width for all masters. Though it would be nice to revisit avr32 plaforms to
>> check what is the actual hardware topology is used there. It seems that it has
>> one bus and two masters on it as stated by Table 8-2, that's why everything
>> works independently on the master in use. The purpose of the sequential patch
>> is to fix the driver for configuration of more that one bus.
>
> Not entirely sure what you want to have confirmed here. There are multiple
> masters and slaves on the HMATRIX internal bus on AVR32, and the DMA
> controller supports up to three simultaneous configurations.
>
> Sounds good to support configuration of more than one bus. I thought we
> always did support that? Perhaps it was a non-standard avr32 implementation.

The DW DMA controller on the AT32AP7000 serves the MCI, AC97, and ABDAC
peripherals.  It appears to work regardless of the values put in the
various master select fields.  Perhaps the topology is hardwired in the
DMA controller and those fields are ignored.  The AVR32 works both
before and after this patch series, the main purpose of which (at least
my patches) is to fix the SATA driver on 460EX.

>> The change is done in the assumption that src_master and dst_master are
>> reflecting a connection to the memory and peripheral correspondently on all
>> platforms except 460ex.
>> 
>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> Signed-off-by: Mans Rullgard <mans@mansr.com>
>
> For the avr32 related stuff:
>
> Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
>
>> ---
>>  Documentation/devicetree/bindings/dma/snps-dma.txt |  4 ++--
>>  arch/avr32/mach-at32ap/at32ap700x.c                | 16 ++++++++--------
>>  drivers/ata/sata_dwc_460ex.c                       |  4 ++--
>>  drivers/dma/dw/core.c                              | 15 +++++++--------
>>  drivers/dma/dw/platform.c                          | 12 ++++++------
>>  drivers/dma/dw/regs.h                              |  4 ++--
>>  drivers/spi/spi-pxa2xx-pci.c                       |  8 ++++----
>>  drivers/tty/serial/8250/8250_pci.c                 |  8 ++++----
>>  include/linux/platform_data/dma-dw.h               |  8 ++++----
>>  9 files changed, 39 insertions(+), 40 deletions(-)
>
> <snipp diff>
>
> -- 
> Best regards, Hans-Christian Egtvedt

-- 
Måns Rullgård

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Hans-Christian Noren Egtvedt]

Around Sun 24 Jan 2016 20:19:46 +0000 or thereabout, Måns Rullgård wrote:
> Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> writes:
>> Around Sun 24 Jan 2016 19:21:50 +0000 or thereabout, Mans Rullgard wrote:
>>> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>>> 
>>> The source and destination masters are reflecting buses or their layers to
>>> where the different devices can be connected. The patch changes the master
>>> names to reflect which one is related to which independently on the transfer
>>> direction.
>>> 
>>> The outcome of the change is that the memory data width is now always limited
>>> by a data width of the master which is dedicated to communicate to memory.
>>> 
>>> The patch will not break anything since all current users have the same data
>>> width for all masters. Though it would be nice to revisit avr32 plaforms to
>>> check what is the actual hardware topology is used there. It seems that it has
>>> one bus and two masters on it as stated by Table 8-2, that's why everything
>>> works independently on the master in use. The purpose of the sequential patch
>>> is to fix the driver for configuration of more that one bus.
>>
>> Not entirely sure what you want to have confirmed here. There are multiple
>> masters and slaves on the HMATRIX internal bus on AVR32, and the DMA
>> controller supports up to three simultaneous configurations.
>>
>> Sounds good to support configuration of more than one bus. I thought we
>> always did support that? Perhaps it was a non-standard avr32 implementation.
> 
> The DW DMA controller on the AT32AP7000 serves the MCI, AC97, and ABDAC
> peripherals.  It appears to work regardless of the values put in the
> various master select fields.  Perhaps the topology is hardwired in the
> DMA controller and those fields are ignored.  The AVR32 works both
> before and after this patch series, the main purpose of which (at least
> my patches) is to fix the SATA driver on 460EX.

DEST_PER and SRC_PER in the DMA controller selects this, numbers placed here
should match the table you most likely found, 9-3.

Wiring the handshake connections is done with the struct dw_dma_slave src_id
or dst_id member, depending on data direction. Configured in the at32ap700x.c
machine code.

It is not hard wired on avr32, as there are not one-to-one configurations and
masters.

>>> The change is done in the assumption that src_master and dst_master are
>>> reflecting a connection to the memory and peripheral correspondently on all
>>> platforms except 460ex.

OK, I have no knowledge about the 460ex.

>>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>>> Signed-off-by: Mans Rullgard <mans@mansr.com>
>>
>> For the avr32 related stuff:
>>
>> Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
>>
>>> ---
>>>  Documentation/devicetree/bindings/dma/snps-dma.txt |  4 ++--
>>>  arch/avr32/mach-at32ap/at32ap700x.c                | 16 ++++++++--------
>>>  drivers/ata/sata_dwc_460ex.c                       |  4 ++--
>>>  drivers/dma/dw/core.c                              | 15 +++++++--------
>>>  drivers/dma/dw/platform.c                          | 12 ++++++------
>>>  drivers/dma/dw/regs.h                              |  4 ++--
>>>  drivers/spi/spi-pxa2xx-pci.c                       |  8 ++++----
>>>  drivers/tty/serial/8250/8250_pci.c                 |  8 ++++----
>>>  include/linux/platform_data/dma-dw.h               |  8 ++++----
>>>  9 files changed, 39 insertions(+), 40 deletions(-)
>>
>> <snipp diff>
-- 
Best regards, Hans-Christian Egtvedt

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Måns Rullgård]

Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> writes:

> Around Sun 24 Jan 2016 20:19:46 +0000 or thereabout, Måns Rullgård wrote:
>> Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> writes:
>>> Around Sun 24 Jan 2016 19:21:50 +0000 or thereabout, Mans Rullgard wrote:
>>>> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>>>> 
>>>> The source and destination masters are reflecting buses or their layers to
>>>> where the different devices can be connected. The patch changes the master
>>>> names to reflect which one is related to which independently on the transfer
>>>> direction.
>>>> 
>>>> The outcome of the change is that the memory data width is now always limited
>>>> by a data width of the master which is dedicated to communicate to memory.
>>>> 
>>>> The patch will not break anything since all current users have the same data
>>>> width for all masters. Though it would be nice to revisit avr32 plaforms to
>>>> check what is the actual hardware topology is used there. It seems that it has
>>>> one bus and two masters on it as stated by Table 8-2, that's why everything
>>>> works independently on the master in use. The purpose of the sequential patch
>>>> is to fix the driver for configuration of more that one bus.
>>>
>>> Not entirely sure what you want to have confirmed here. There are multiple
>>> masters and slaves on the HMATRIX internal bus on AVR32, and the DMA
>>> controller supports up to three simultaneous configurations.
>>>
>>> Sounds good to support configuration of more than one bus. I thought we
>>> always did support that? Perhaps it was a non-standard avr32 implementation.
>> 
>> The DW DMA controller on the AT32AP7000 serves the MCI, AC97, and ABDAC
>> peripherals.  It appears to work regardless of the values put in the
>> various master select fields.  Perhaps the topology is hardwired in the
>> DMA controller and those fields are ignored.  The AVR32 works both
>> before and after this patch series, the main purpose of which (at least
>> my patches) is to fix the SATA driver on 460EX.
>
> DEST_PER and SRC_PER in the DMA controller selects this, numbers placed here
> should match the table you most likely found, 9-3.
>
> Wiring the handshake connections is done with the struct dw_dma_slave src_id
> or dst_id member, depending on data direction. Configured in the at32ap700x.c
> machine code.
>
> It is not hard wired on avr32, as there are not one-to-one configurations and
> masters.

This is about the SMS (Source Master Select) and DMS (Destination Master
Select) fields in the CTLxL register and the LMS (List Master Select)
field in the LLPx register.

>>>> The change is done in the assumption that src_master and dst_master are
>>>> reflecting a connection to the memory and peripheral correspondently on all
>>>> platforms except 460ex.
>
> OK, I have no knowledge about the 460ex.
>
>>>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>>>> Signed-off-by: Mans Rullgard <mans@mansr.com>
>>>
>>> For the avr32 related stuff:
>>>
>>> Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
>>>
>>>> ---
>>>>  Documentation/devicetree/bindings/dma/snps-dma.txt |  4 ++--
>>>>  arch/avr32/mach-at32ap/at32ap700x.c                | 16 ++++++++--------
>>>>  drivers/ata/sata_dwc_460ex.c                       |  4 ++--
>>>>  drivers/dma/dw/core.c                              | 15 +++++++--------
>>>>  drivers/dma/dw/platform.c                          | 12 ++++++------
>>>>  drivers/dma/dw/regs.h                              |  4 ++--
>>>>  drivers/spi/spi-pxa2xx-pci.c                       |  8 ++++----
>>>>  drivers/tty/serial/8250/8250_pci.c                 |  8 ++++----
>>>>  include/linux/platform_data/dma-dw.h               |  8 ++++----
>>>>  9 files changed, 39 insertions(+), 40 deletions(-)
>>>
>>> <snipp diff>
> -- 
> Best regards, Hans-Christian Egtvedt

-- 
Måns Rullgård

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 543 bytes --]

On Sun, Jan 24, 2016 at 07:21:50PM +0000, Mans Rullgard wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> The source and destination masters are reflecting buses or their layers to
> where the different devices can be connected. The patch changes the master
> names to reflect which one is related to which independently on the transfer
> direction.

This is patch 3 of a series but I don't have anything else in the
series.  What is going on with the rest of the series - what are the
dependencies and so on?

[-- Attachment #2: signature.asc --]
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Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Måns Rullgård]

Mark Brown <broonie@kernel.org> writes:

> On Sun, Jan 24, 2016 at 07:21:50PM +0000, Mans Rullgard wrote:
>> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> 
>> The source and destination masters are reflecting buses or their layers to
>> where the different devices can be connected. The patch changes the master
>> names to reflect which one is related to which independently on the transfer
>> direction.
>
> This is patch 3 of a series but I don't have anything else in the
> series.  What is going on with the rest of the series - what are the
> dependencies and so on?

I give up.  Seriously, this is impossible.  If I don't include everybody
in the slightest way related to any patch in the series, I get
complaints that patches are missing.  If I do, the lists reject it all
due to too many recipients.  What the hell am I supposed to do?

-- 
Måns Rullgård

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Viresh Kumar]

On 24-01-16, 22:38, Måns Rullgård wrote:
> I give up.  Seriously, this is impossible.  If I don't include everybody
> in the slightest way related to any patch in the series, I get
> complaints that patches are missing.  If I do, the lists reject it all
> due to too many recipients.  What the hell am I supposed to do?

Bcc everyone and mention that in cover-letter :)

-- 
viresh

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Vinod Koul]

On Sun, Jan 24, 2016 at 10:38:57PM +0000, Måns Rullgård wrote:
> Mark Brown <broonie@kernel.org> writes:
> 
> > On Sun, Jan 24, 2016 at 07:21:50PM +0000, Mans Rullgard wrote:
> >> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >> 
> >> The source and destination masters are reflecting buses or their layers to
> >> where the different devices can be connected. The patch changes the master
> >> names to reflect which one is related to which independently on the transfer
> >> direction.
> >
> > This is patch 3 of a series but I don't have anything else in the
> > series.  What is going on with the rest of the series - what are the
> > dependencies and so on?
> 
> I give up.  Seriously, this is impossible.  If I don't include everybody
> in the slightest way related to any patch in the series, I get
> complaints that patches are missing.  If I do, the lists reject it all
> due to too many recipients.  What the hell am I supposed to do?

Right practice is to CC everyone in cover-letter and mention which subsystem
this is intended to be merged thru and CC relevant folks on the patches.

That gives everyone context and right attention and lesser noise on patches

-- 
~Vinod

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 914 bytes --]

On Sun, Jan 24, 2016 at 10:38:57PM +0000, Måns Rullgård wrote:
> Mark Brown <broonie@kernel.org> writes:

> > This is patch 3 of a series but I don't have anything else in the
> > series.  What is going on with the rest of the series - what are the
> > dependencies and so on?

> I give up.  Seriously, this is impossible.  If I don't include everybody
> in the slightest way related to any patch in the series, I get
> complaints that patches are missing.  If I do, the lists reject it all
> due to too many recipients.  What the hell am I supposed to do?

You should normally include at least the subsystem maintainers in at
least the cover letter and cover the dependencies there.  Think about
how this is going to work: if you don't give us any information on
what's going on with dependencies then we can't tell how to handle the
patches - do we need to apply them, only review them or what?

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Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Andy Shevchenko]

On Sun, 2016-01-24 at 22:36 +0000, Mark Brown wrote:
> On Sun, Jan 24, 2016 at 07:21:50PM +0000, Mans Rullgard wrote:
> > From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > 
> > The source and destination masters are reflecting buses or their
> > layers to
> > where the different devices can be connected. The patch changes the
> > master
> > names to reflect which one is related to which independently on the
> > transfer
> > direction.
> 
> This is patch 3 of a series but I don't have anything else in the
> series.  What is going on with the rest of the series - what are the
> dependencies and so on?

Mark, sorry about that, but in this particular case you may consider
this patch is a standalone one. You are in the Cc list due to SPI
driver small change. This change isn't modifying functionality of the
driver.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 596 bytes --]

On Mon, Jan 25, 2016 at 10:35:02AM +0200, Andy Shevchenko wrote:
> On Sun, 2016-01-24 at 22:36 +0000, Mark Brown wrote:

> > This is patch 3 of a series but I don't have anything else in the
> > series.  What is going on with the rest of the series - what are the
> > dependencies and so on?

> Mark, sorry about that, but in this particular case you may consider
> this patch is a standalone one. You are in the Cc list due to SPI
> driver small change. This change isn't modifying functionality of the
> driver.

And there's no dependency relationship with the rest of the series?

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Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Andy Shevchenko]

On Mon, 2016-01-25 at 12:24 +0000, Mark Brown wrote:
> On Mon, Jan 25, 2016 at 10:35:02AM +0200, Andy Shevchenko wrote:
> > On Sun, 2016-01-24 at 22:36 +0000, Mark Brown wrote:
> 
> > > This is patch 3 of a series but I don't have anything else in the
> > > series.  What is going on with the rest of the series - what are
> > > the
> > > dependencies and so on?
> 
> > Mark, sorry about that, but in this particular case you may
> > consider
> > this patch is a standalone one. You are in the Cc list due to SPI
> > driver small change. This change isn't modifying functionality of
> > the
> > driver.
> 
> And there's no dependency relationship with the rest of the series?

Yes, in this particular case. To confirm I even rebased locally the
series to be 100% sure.

The complete series can be found in
https://bitbucket.org/mansr/linux-dwc/branch/dwc-sata

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 03/15] dmaengine: dw: rename masters to reflect actual topology

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 424 bytes --]

On Sun, Jan 24, 2016 at 07:21:50PM +0000, Mans Rullgard wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> The source and destination masters are reflecting buses or their layers to
> where the different devices can be connected. The patch changes the master
> names to reflect which one is related to which independently on the transfer
> direction.

Acked-by: Mark Brown <broonie@kernel.org>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]

[PATCH 04/15] dmaengine: dw: set src and dst master select according to xfer direction

[Mans Rullgard]

On some architectures the DMA controller can have two masters connected to
different buses and thus access to memory is possible only through one and
to peripheral through the other.

This patch changes the src and dst master setting to match the direction
of the transfer.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 8d1b87ff2ac6..1e29efad2bf1 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -45,13 +45,17 @@
 			DW_DMA_MSIZE_16;			\
 		u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :	\
 			DW_DMA_MSIZE_16;			\
+		u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ?		\
+			_dwc->p_master : _dwc->m_master;		\
+		u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ?		\
+			_dwc->p_master : _dwc->m_master;		\
 								\
 		(DWC_CTLL_DST_MSIZE(_dmsize)			\
 		 | DWC_CTLL_SRC_MSIZE(_smsize)			\
 		 | DWC_CTLL_LLP_D_EN				\
 		 | DWC_CTLL_LLP_S_EN				\
-		 | DWC_CTLL_DMS(_dwc->p_master)			\
-		 | DWC_CTLL_SMS(_dwc->m_master));		\
+		 | DWC_CTLL_DMS(_dms)				\
+		 | DWC_CTLL_SMS(_sms));				\
 	})
 
 /*
-- 
2.7.0

[PATCH 05/15] dmaengine: dw: set LMS field in descriptors

[Mans Rullgard]

The LMS field indicates from which master the descriptor is to be
read.  This patch assumes this is always the same as the memory
side in a peripheral transfer which is true for all known systems.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/dw/core.c | 19 +++++++++----------
 drivers/dma/dw/regs.h |  4 ++++
 2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 1e29efad2bf1..bbae43451529 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -265,7 +265,7 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 
 	dwc_initialize(dwc);
 
-	channel_writel(dwc, LLP, first->txd.phys);
+	channel_writel(dwc, LLP, first->txd.phys | DWC_LLP_LMS(dwc->m_master));
 	channel_writel(dwc, CTL_LO,
 			DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 	channel_writel(dwc, CTL_HI, 0);
@@ -431,7 +431,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 		dwc->residue = desc->total_len;
 
 		/* Check first descriptors addr */
-		if (desc->txd.phys == llp) {
+		if (desc->txd.phys == DWC_LLP_LOC(llp)) {
 			spin_unlock_irqrestore(&dwc->lock, flags);
 			return;
 		}
@@ -756,7 +756,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 		if (!first) {
 			first = desc;
 		} else {
-			lli_write(prev, llp, desc->txd.phys);
+			lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));
 			list_add_tail(&desc->desc_node, &first->tx_list);
 		}
 		prev = desc;
@@ -853,7 +853,7 @@ slave_sg_todev_fill_desc:
 			if (!first) {
 				first = desc;
 			} else {
-				lli_write(prev, llp, desc->txd.phys);
+				lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));
 				list_add_tail(&desc->desc_node, &first->tx_list);
 			}
 			prev = desc;
@@ -908,7 +908,7 @@ slave_sg_fromdev_fill_desc:
 			if (!first) {
 				first = desc;
 			} else {
-				lli_write(prev, llp, desc->txd.phys);
+				lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));
 				list_add_tail(&desc->desc_node, &first->tx_list);
 			}
 			prev = desc;
@@ -1427,13 +1427,13 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
 		cdesc->desc[i] = desc;
 
 		if (last)
-			lli_write(last, llp, desc->txd.phys);
+			lli_write(last, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));
 
 		last = desc;
 	}
 
 	/* Let's make a cyclic list */
-	lli_write(last, llp, cdesc->desc[0]->txd.phys);
+	lli_write(last, llp, cdesc->desc[0]->txd.phys | DWC_LLP_LMS(dwc->m_master));
 
 	dev_dbg(chan2dev(&dwc->chan),
 			"cyclic prepared buf %pad len %zu period %zu periods %d\n",
@@ -1635,9 +1635,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 			dwc->block_size = pdata->block_size;
 
 			/* Check if channel supports multi block transfer */
-			channel_writel(dwc, LLP, 0xfffffffc);
-			dwc->nollp =
-				(channel_readl(dwc, LLP) & 0xfffffffc) == 0;
+			channel_writel(dwc, LLP, 0xffffffff);
+			dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
 			channel_writel(dwc, LLP, 0);
 		}
 	}
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 0391f8ff6919..4e6ec2d75863 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -143,6 +143,10 @@ enum dw_dma_msize {
 	DW_DMA_MSIZE_256,
 };
 
+/* Bitfields in LLP */
+#define DWC_LLP_LMS(x)		((x) & 3)	/* list master select */
+#define DWC_LLP_LOC(x)		((x) & ~3)	/* next lli */
+
 /* Bitfields in CTL_LO */
 #define DWC_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
 #define DWC_CTLL_DST_WIDTH(n)	((n)<<1)	/* bytes per element */
-- 
2.7.0

[PATCH 06/15] dmaengine: dw: substitute dma_read_byaddr by dma_readl_native

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Since struct dw_dma is allocated and regs member is assigned properly we can
use standard IO accessors to the DMA registers.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 8 +++-----
 drivers/dma/dw/regs.h | 4 ----
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index bbae43451529..140ea59ec882 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1513,7 +1513,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 	pm_runtime_get_sync(chip->dev);
 
 	if (!pdata) {
-		dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
+		dw_params = dma_readl(dw, DW_PARAMS);
 		dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
 
 		autocfg = dw_params >> DW_PARAMS_EN & 1;
@@ -1613,11 +1613,9 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 
 		/* Hardware configuration */
 		if (autocfg) {
-			unsigned int dwc_params;
 			unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
-			void __iomem *addr = chip->regs + r * sizeof(u32);
-
-			dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
+			void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
+			unsigned int dwc_params = dma_readl_native(addr);
 
 			dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
 					   dwc_params);
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 4e6ec2d75863..e4b277565165 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -114,10 +114,6 @@ struct dw_dma_regs {
 #define dma_writel_native writel
 #endif
 
-/* To access the registers in early stage of probe */
-#define dma_read_byaddr(addr, name) \
-	dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
-
 /* Bitfields in DW_PARAMS */
 #define DW_PARAMS_NR_CHAN	8		/* number of channels */
 #define DW_PARAMS_NR_MASTER	11		/* number of AHB masters */
-- 
2.7.0

[PATCH 07/15] dmaengine: dw: revisit data_width property

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

There are several changes are done here:

 - Convert the property to be in bytes

   Much more convenient than keeping encoded value.

 - Use one value for all AHB masters for now

   It seems in practice we have no controllers where masters have different
   data bus width, we still might return to distinct values when there is a use
   case.

 - Rename data_width to data-width in the device tree bindings.

 - While here, replace dwc_fast_ffs() by __ffs().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
This patch changes the DT binding, so it should probably be amended for
compatibility with old device trees.  I've included it as is since I think
the change as such is good.
---
 Documentation/devicetree/bindings/dma/snps-dma.txt |  5 ++-
 arch/arc/boot/dts/abilis_tb10x.dtsi                |  2 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |  4 +--
 drivers/dma/dw/core.c                              | 40 +++-------------------
 drivers/dma/dw/platform.c                          |  8 ++---
 drivers/dma/dw/regs.h                              |  2 +-
 include/linux/platform_data/dma-dw.h               |  5 ++-
 7 files changed, 16 insertions(+), 50 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
index c99c1ffac199..fe7f7710a6b4 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -13,8 +13,7 @@ Required properties:
 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
   increase from chan n->0
 - block_size: Maximum block size supported by the controller
-- data_width: Maximum data width supported by hardware per AHB master
-  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
+- data-width: Maximum data width supported by hardware (in bytes)
 
 
 Optional properties:
@@ -38,7 +37,7 @@ Example:
 		chan_allocation_order = <1>;
 		chan_priority = <1>;
 		block_size = <0xfff>;
-		data_width = <3 3>;
+		data-width = <8>;
 	};
 
 DMA clients connected to the Designware DMA controller must use the format
diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
index cfb5052239a1..2f53bedb0cde 100644
--- a/arch/arc/boot/dts/abilis_tb10x.dtsi
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -112,7 +112,7 @@
 			chan_allocation_order = <0>;
 			chan_priority = <1>;
 			block_size = <0x7ff>;
-			data_width = <2>;
+			data-width = <4>;
 			clocks = <&ahb_clk>;
 			clock-names = "hclk";
 		};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 14594ce8c18a..474b66fa6a32 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -117,7 +117,7 @@
 			chan_priority = <1>;
 			block_size = <0xfff>;
 			dma-masters = <2>;
-			data_width = <3 3>;
+			data-width = <8>;
 		};
 
 		dma@eb000000 {
@@ -133,7 +133,7 @@
 			chan_allocation_order = <1>;
 			chan_priority = <1>;
 			block_size = <0xfff>;
-			data_width = <3 3>;
+			data-width = <8>;
 		};
 
 		fsmc: flash@b0000000 {
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 140ea59ec882..28278e4c77ad 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -168,21 +168,6 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
 
 /*----------------------------------------------------------------------*/
 
-static inline unsigned int dwc_fast_ffs(unsigned long long v)
-{
-	/*
-	 * We can be a lot more clever here, but this should take care
-	 * of the most common optimization.
-	 */
-	if (!(v & 7))
-		return 3;
-	else if (!(v & 3))
-		return 2;
-	else if (!(v & 1))
-		return 1;
-	return 0;
-}
-
 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 {
 	dev_err(chan2dev(&dwc->chan),
@@ -712,7 +697,6 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 	size_t			offset;
 	unsigned int		src_width;
 	unsigned int		dst_width;
-	unsigned int		data_width;
 	u32			ctllo;
 
 	dev_vdbg(chan2dev(chan),
@@ -726,10 +710,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 
 	dwc->direction = DMA_MEM_TO_MEM;
 
-	data_width = dw->data_width[dwc->m_master];
-
-	src_width = dst_width = min_t(unsigned int, data_width,
-				      dwc_fast_ffs(src | dest | len));
+	src_width = dst_width = __ffs(dw->data_width | src | dest | len);
 
 	ctllo = DWC_DEFAULT_CTLLO(chan)
 			| DWC_CTLL_DST_WIDTH(dst_width)
@@ -792,7 +773,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 	dma_addr_t		reg;
 	unsigned int		reg_width;
 	unsigned int		mem_width;
-	unsigned int		data_width;
 	unsigned int		i;
 	struct scatterlist	*sg;
 	size_t			total_len = 0;
@@ -818,8 +798,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 		ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 			DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 
-		data_width = dw->data_width[dwc->m_master];
-
 		for_each_sg(sgl, sg, sg_len, i) {
 			struct dw_desc	*desc;
 			u32		len, dlen, mem;
@@ -827,8 +805,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 			mem = sg_dma_address(sg);
 			len = sg_dma_len(sg);
 
-			mem_width = min_t(unsigned int,
-					  data_width, dwc_fast_ffs(mem | len));
+			mem_width = __ffs(dw->data_width | mem | len);
 
 slave_sg_todev_fill_desc:
 			desc = dwc_desc_get(dwc);
@@ -874,8 +851,6 @@ slave_sg_todev_fill_desc:
 		ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 			DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 
-		data_width = dw->data_width[dwc->m_master];
-
 		for_each_sg(sgl, sg, sg_len, i) {
 			struct dw_desc	*desc;
 			u32		len, dlen, mem;
@@ -883,8 +858,7 @@ slave_sg_todev_fill_desc:
 			mem = sg_dma_address(sg);
 			len = sg_dma_len(sg);
 
-			mem_width = min_t(unsigned int,
-					  data_width, dwc_fast_ffs(mem | len));
+			mem_width = __ffs(dw->data_width | mem | len);
 
 slave_sg_fromdev_fill_desc:
 			desc = dwc_desc_get(dwc);
@@ -1531,10 +1505,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 		/* Get hardware configuration parameters */
 		pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
 		pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
-		for (i = 0; i < pdata->nr_masters; i++) {
-			pdata->data_width[i] =
-				(dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
-		}
+		pdata->data_width = 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(0) & 3);
 		max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
 
 		/* Fill platform data with the default values */
@@ -1556,8 +1527,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 
 	/* Get hardware configuration parameters */
 	dw->nr_masters = pdata->nr_masters;
-	for (i = 0; i < dw->nr_masters; i++)
-		dw->data_width[i] = pdata->data_width[i];
+	dw->data_width = pdata->data_width;
 
 	/* Calculate all channel mask before DMA setup */
 	dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index d3e1abcebd7f..89d0461f5dcc 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -102,8 +102,8 @@ dw_dma_parse_dt(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
 	struct dw_dma_platform_data *pdata;
-	u32 tmp, arr[DW_DMA_MAX_NR_MASTERS];
 	u32 nr_channels;
+	u32 tmp;
 
 	if (!np) {
 		dev_err(&pdev->dev, "Missing DT data\n");
@@ -138,10 +138,8 @@ dw_dma_parse_dt(struct platform_device *pdev)
 		pdata->nr_masters = tmp;
 	}
 
-	if (!of_property_read_u32_array(np, "data_width", arr,
-				pdata->nr_masters))
-		for (tmp = 0; tmp < pdata->nr_masters; tmp++)
-			pdata->data_width[tmp] = arr[tmp];
+	if (!of_property_read_u32(np, "data-width", &tmp))
+		pdata->data_width = tmp;
 
 	return pdata;
 }
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index e4b277565165..87bc97fca084 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -285,7 +285,7 @@ struct dw_dma {
 
 	/* hardware configuration */
 	unsigned char		nr_masters;
-	unsigned char		data_width[DW_DMA_MAX_NR_MASTERS];
+	unsigned char		data_width;
 };
 
 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index b881b978e486..4120a3eb71ca 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -42,8 +42,7 @@ struct dw_dma_slave {
  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  * @block_size: Maximum block size supported by the controller
  * @nr_masters: Number of AHB masters supported by the controller
- * @data_width: Maximum data width supported by hardware per AHB master
- *		(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
+ * @data_width: Maximum data width supported by hardware (in bytes)
  */
 struct dw_dma_platform_data {
 	unsigned int	nr_channels;
@@ -57,7 +56,7 @@ struct dw_dma_platform_data {
 	unsigned char	chan_priority;
 	unsigned short	block_size;
 	unsigned char	nr_masters;
-	unsigned char	data_width[DW_DMA_MAX_NR_MASTERS];
+	unsigned char	data_width;
 };
 
 #endif /* _PLATFORM_DATA_DMA_DW_H */
-- 
2.7.0

Re: [PATCH 07/15] dmaengine: dw: revisit data_width property

[Vineet Gupta]

On Monday 25 January 2016 12:55 AM, Mans Rullgard wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> There are several changes are done here:
>
>  - Convert the property to be in bytes
>
>    Much more convenient than keeping encoded value.
>
>  - Use one value for all AHB masters for now
>
>    It seems in practice we have no controllers where masters have different
>    data bus width, we still might return to distinct values when there is a use
>    case.
>
>  - Rename data_width to data-width in the device tree bindings.
>
>  - While here, replace dwc_fast_ffs() by __ffs().
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> This patch changes the DT binding, so it should probably be amended for
> compatibility with old device trees.  I've included it as is since I think
> the change as such is good.
> ---
>  Documentation/devicetree/bindings/dma/snps-dma.txt |  5 ++-
>  arch/arc/boot/dts/abilis_tb10x.dtsi                |  2 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |  4 +--
>  drivers/dma/dw/core.c                              | 40 +++-------------------
>  drivers/dma/dw/platform.c                          |  8 ++---
>  drivers/dma/dw/regs.h                              |  2 +-
>  include/linux/platform_data/dma-dw.h               |  5 ++-
>  7 files changed, 16 insertions(+), 50 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
> index c99c1ffac199..fe7f7710a6b4 100644
> --- a/Documentation/devicetree/bindings/dma/snps-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
> @@ -13,8 +13,7 @@ Required properties:
>  - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
>    increase from chan n->0
>  - block_size: Maximum block size supported by the controller
> -- data_width: Maximum data width supported by hardware per AHB master
> -  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
> +- data-width: Maximum data width supported by hardware (in bytes)

To the reader this suggests a value truely byte granular, but code uses ffs
implying that it is still power of 2.
Can you mention this here (....in bytes, always power of 2).

> ...
> @@ -726,10 +710,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
>  
>  	dwc->direction = DMA_MEM_TO_MEM;
>  
> -	data_width = dw->data_width[dwc->m_master];
> -
> -	src_width = dst_width = min_t(unsigned int, data_width,
> -				      dwc_fast_ffs(src | dest | len));
> +	src_width = dst_width = __ffs(dw->data_width | src | dest | len);
> ...

-Vineet

Re: [PATCH 07/15] dmaengine: dw: revisit data_width property

[Andy Shevchenko]

On Mon, 2016-01-25 at 07:32 +0000, Vineet Gupta wrote:
> On Monday 25 January 2016 12:55 AM, Mans Rullgard wrote:
> > From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > 
> > There are several changes are done here:
> > 
> >  - Convert the property to be in bytes
> > 
> >    Much more convenient than keeping encoded value.
> > 
> >  - Use one value for all AHB masters for now
> > 
> >    It seems in practice we have no controllers where masters have
> > different
> >    data bus width, we still might return to distinct values when
> > there is a use
> >    case.
> > 
> >  - Rename data_width to data-width in the device tree bindings.
> > 
> >  - While here, replace dwc_fast_ffs() by __ffs().
> > 
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Signed-off-by: Mans Rullgard <mans@mansr.com>
> > ---
> > This patch changes the DT binding, so it should probably be amended
> > for
> > compatibility with old device trees.  I've included it as is since
> > I think
> > the change as such is good.
> > ---
> >  Documentation/devicetree/bindings/dma/snps-dma.txt |  5 ++-
> >  arch/arc/boot/dts/abilis_tb10x.dtsi                |  2 +-
> >  arch/arm/boot/dts/spear13xx.dtsi                   |  4 +--
> >  drivers/dma/dw/core.c                              | 40 +++-------
> > ------------
> >  drivers/dma/dw/platform.c                          |  8 ++---
> >  drivers/dma/dw/regs.h                              |  2 +-
> >  include/linux/platform_data/dma-dw.h               |  5 ++-
> >  7 files changed, 16 insertions(+), 50 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt
> > b/Documentation/devicetree/bindings/dma/snps-dma.txt
> > index c99c1ffac199..fe7f7710a6b4 100644
> > --- a/Documentation/devicetree/bindings/dma/snps-dma.txt
> > +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
> > @@ -13,8 +13,7 @@ Required properties:
> >  - chan_priority: priority of channels. 0 (default): increase from
> > chan 0->n, 1:
> >    increase from chan n->0
> >  - block_size: Maximum block size supported by the controller
> > -- data_width: Maximum data width supported by hardware per AHB
> > master
> > -  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
> > +- data-width: Maximum data width supported by hardware (in bytes)
> 
> To the reader this suggests a value truely byte granular, but code
> uses ffs
> implying that it is still power of 2.
> Can you mention this here (....in bytes, always power of 2).

While this comment is good, I have still note that using non-power of 2
values will not break anything. Least power of two number will be used
in that case. So, means I would suggest to replace 'always' by 'better
to be' or something like that.

> 
> > ...
> > @@ -726,10 +710,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan,
> > dma_addr_t dest, dma_addr_t src,
> >  
> >  	dwc->direction = DMA_MEM_TO_MEM;
> >  
> > -	data_width = dw->data_width[dwc->m_master];
> > -
> > -	src_width = dst_width = min_t(unsigned int, data_width,
> > -				      dwc_fast_ffs(src | dest |
> > len));
> > +	src_width = dst_width = __ffs(dw->data_width | src | dest
> > | len);
> > ...
> 
> -Vineet

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 07/15] dmaengine: dw: revisit data_width property

[Måns Rullgård]

Andy Shevchenko <andriy.shevchenko@linux.intel.com> writes:

> On Mon, 2016-01-25 at 07:32 +0000, Vineet Gupta wrote:
>> On Monday 25 January 2016 12:55 AM, Mans Rullgard wrote:
>> > From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> > 
>> > There are several changes are done here:
>> > 
>> >  - Convert the property to be in bytes
>> > 
>> >    Much more convenient than keeping encoded value.
>> > 
>> >  - Use one value for all AHB masters for now
>> > 
>> >    It seems in practice we have no controllers where masters have
>> > different
>> >    data bus width, we still might return to distinct values when
>> > there is a use
>> >    case.
>> > 
>> >  - Rename data_width to data-width in the device tree bindings.
>> > 
>> >  - While here, replace dwc_fast_ffs() by __ffs().
>> > 
>> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> > Signed-off-by: Mans Rullgard <mans@mansr.com>
>> > ---
>> > This patch changes the DT binding, so it should probably be amended
>> > for
>> > compatibility with old device trees.  I've included it as is since
>> > I think
>> > the change as such is good.
>> > ---
>> >  Documentation/devicetree/bindings/dma/snps-dma.txt |  5 ++-
>> >  arch/arc/boot/dts/abilis_tb10x.dtsi                |  2 +-
>> >  arch/arm/boot/dts/spear13xx.dtsi                   |  4 +--
>> >  drivers/dma/dw/core.c                              | 40 +++-------
>> > ------------
>> >  drivers/dma/dw/platform.c                          |  8 ++---
>> >  drivers/dma/dw/regs.h                              |  2 +-
>> >  include/linux/platform_data/dma-dw.h               |  5 ++-
>> >  7 files changed, 16 insertions(+), 50 deletions(-)
>> > 
>> > diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt
>> > b/Documentation/devicetree/bindings/dma/snps-dma.txt
>> > index c99c1ffac199..fe7f7710a6b4 100644
>> > --- a/Documentation/devicetree/bindings/dma/snps-dma.txt
>> > +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
>> > @@ -13,8 +13,7 @@ Required properties:
>> >  - chan_priority: priority of channels. 0 (default): increase from
>> > chan 0->n, 1:
>> >    increase from chan n->0
>> >  - block_size: Maximum block size supported by the controller
>> > -- data_width: Maximum data width supported by hardware per AHB
>> > master
>> > -  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
>> > +- data-width: Maximum data width supported by hardware (in bytes)
>> 
>> To the reader this suggests a value truely byte granular, but code
>> uses ffs
>> implying that it is still power of 2.
>> Can you mention this here (....in bytes, always power of 2).
>
> While this comment is good, I have still note that using non-power of 2
> values will not break anything. Least power of two number will be used
> in that case. So, means I would suggest to replace 'always' by 'better
> to be' or something like that.

Although the code rounds down, the hardware actually works in powers of
two, and it's better to document this.

-- 
Måns Rullgård

Re: [PATCH 07/15] dmaengine: dw: revisit data_width property

[Andy Shevchenko]

On Mon, 2016-01-25 at 10:31 +0000, Måns Rullgård wrote:
> Andy Shevchenko <andriy.shevchenko@linux.intel.com> writes:
> 
> > On Mon, 2016-01-25 at 07:32 +0000, Vineet Gupta wrote:
> > > On Monday 25 January 2016 12:55 AM, Mans Rullgard wrote:

> > > > --- a/Documentation/devicetree/bindings/dma/snps-dma.txt
> > > > +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
> > > > @@ -13,8 +13,7 @@ Required properties:
> > > >  - chan_priority: priority of channels. 0 (default): increase
> > > > from
> > > > chan 0->n, 1:
> > > >    increase from chan n->0
> > > >  - block_size: Maximum block size supported by the controller
> > > > -- data_width: Maximum data width supported by hardware per AHB
> > > > master
> > > > -  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
> > > > +- data-width: Maximum data width supported by hardware (in
> > > > bytes)
> > > 
> > > To the reader this suggests a value truely byte granular, but
> > > code
> > > uses ffs
> > > implying that it is still power of 2.
> > > Can you mention this here (....in bytes, always power of 2).
> > 
> > While this comment is good, I have still note that using non-power
> > of 2
> > values will not break anything. Least power of two number will be
> > used
> > in that case. So, means I would suggest to replace 'always' by
> > 'better
> > to be' or something like that.
> 
> Although the code rounds down, the hardware actually works in powers
> of
> two, and it's better to document this.

Let's do "(in bytes, power of 2)" then?

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 07/15] dmaengine: dw: revisit data_width property

[Andy Shevchenko]

On Sun, 2016-01-24 at 19:21 +0000, Mans Rullgard wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> There are several changes are done here:
> 
>  - Convert the property to be in bytes
> 
>    Much more convenient than keeping encoded value.
> 
>  - Use one value for all AHB masters for now
> 
>    It seems in practice we have no controllers where masters have
> different
>    data bus width, we still might return to distinct values when
> there is a use
>    case.
> 
>  - Rename data_width to data-width in the device tree bindings.
> 
>  - While here, replace dwc_fast_ffs() by __ffs().
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> This patch changes the DT binding, so it should probably be amended
> for
> compatibility with old device trees.  I've included it as is since I
> think
> the change as such is good.

So, since all users have at least one master defined, we may easily to
use similar line for old DT variable

if (!of_property_read_u32(np, "data_width", &tmp)) /* removeme: old */
	
pdata->data_width = tmp;
else if (!of_property_read_u32(np, "data-
width", &tmp)) /* removeme: new */
	pdata->data_width = tmp;

I any case Viresh might comment on this since it was his code regarding
to support SPEAr SoCs.

> ---
>  Documentation/devicetree/bindings/dma/snps-dma.txt |  5 ++-
>  arch/arc/boot/dts/abilis_tb10x.dtsi                |  2 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |  4 +--
>  drivers/dma/dw/core.c                              | 40 +++---------
> ----------
>  drivers/dma/dw/platform.c                          |  8 ++---
>  drivers/dma/dw/regs.h                              |  2 +-
>  include/linux/platform_data/dma-dw.h               |  5 ++-
>  7 files changed, 16 insertions(+), 50 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt
> b/Documentation/devicetree/bindings/dma/snps-dma.txt
> index c99c1ffac199..fe7f7710a6b4 100644
> --- a/Documentation/devicetree/bindings/dma/snps-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
> @@ -13,8 +13,7 @@ Required properties:
>  - chan_priority: priority of channels. 0 (default): increase from
> chan 0->n, 1:
>    increase from chan n->0
>  - block_size: Maximum block size supported by the controller
> -- data_width: Maximum data width supported by hardware per AHB
> master
> -  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
> +- data-width: Maximum data width supported by hardware (in bytes)
>  
>  
>  Optional properties:
> @@ -38,7 +37,7 @@ Example:
>  		chan_allocation_order = <1>;
>  		chan_priority = <1>;
>  		block_size = <0xfff>;
> -		data_width = <3 3>;
> +		data-width = <8>;
>  	};
>  
>  DMA clients connected to the Designware DMA controller must use the
> format
> diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi
> b/arch/arc/boot/dts/abilis_tb10x.dtsi
> index cfb5052239a1..2f53bedb0cde 100644
> --- a/arch/arc/boot/dts/abilis_tb10x.dtsi
> +++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
> @@ -112,7 +112,7 @@
>  			chan_allocation_order = <0>;
>  			chan_priority = <1>;
>  			block_size = <0x7ff>;
> -			data_width = <2>;
> +			data-width = <4>;
>  			clocks = <&ahb_clk>;
>  			clock-names = "hclk";
>  		};
> diff --git a/arch/arm/boot/dts/spear13xx.dtsi
> b/arch/arm/boot/dts/spear13xx.dtsi
> index 14594ce8c18a..474b66fa6a32 100644
> --- a/arch/arm/boot/dts/spear13xx.dtsi
> +++ b/arch/arm/boot/dts/spear13xx.dtsi
> @@ -117,7 +117,7 @@
>  			chan_priority = <1>;
>  			block_size = <0xfff>;
>  			dma-masters = <2>;
> -			data_width = <3 3>;
> +			data-width = <8>;
>  		};
>  
>  		dma@eb000000 {
> @@ -133,7 +133,7 @@
>  			chan_allocation_order = <1>;
>  			chan_priority = <1>;
>  			block_size = <0xfff>;
> -			data_width = <3 3>;
> +			data-width = <8>;
>  		};
>  
>  		fsmc: flash@b0000000 {
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index 140ea59ec882..28278e4c77ad 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -168,21 +168,6 @@ static void dwc_initialize(struct dw_dma_chan
> *dwc)
>  
>  /*----------------------------------------------------------------
> ------*/
>  
> -static inline unsigned int dwc_fast_ffs(unsigned long long v)
> -{
> -	/*
> -	 * We can be a lot more clever here, but this should take
> care
> -	 * of the most common optimization.
> -	 */
> -	if (!(v & 7))
> -		return 3;
> -	else if (!(v & 3))
> -		return 2;
> -	else if (!(v & 1))
> -		return 1;
> -	return 0;
> -}
> -
>  static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
>  {
>  	dev_err(chan2dev(&dwc->chan),
> @@ -712,7 +697,6 @@ dwc_prep_dma_memcpy(struct dma_chan *chan,
> dma_addr_t dest, dma_addr_t src,
>  	size_t			offset;
>  	unsigned int		src_width;
>  	unsigned int		dst_width;
> -	unsigned int		data_width;
>  	u32			ctllo;
>  
>  	dev_vdbg(chan2dev(chan),
> @@ -726,10 +710,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan,
> dma_addr_t dest, dma_addr_t src,
>  
>  	dwc->direction = DMA_MEM_TO_MEM;
>  
> -	data_width = dw->data_width[dwc->m_master];
> -
> -	src_width = dst_width = min_t(unsigned int, data_width,
> -				      dwc_fast_ffs(src | dest |
> len));
> +	src_width = dst_width = __ffs(dw->data_width | src | dest |
> len);
>  
>  	ctllo = DWC_DEFAULT_CTLLO(chan)
>  			| DWC_CTLL_DST_WIDTH(dst_width)
> @@ -792,7 +773,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct
> scatterlist *sgl,
>  	dma_addr_t		reg;
>  	unsigned int		reg_width;
>  	unsigned int		mem_width;
> -	unsigned int		data_width;
>  	unsigned int		i;
>  	struct scatterlist	*sg;
>  	size_t			total_len = 0;
> @@ -818,8 +798,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct
> scatterlist *sgl,
>  		ctllo |= sconfig->device_fc ?
> DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
>  			DWC_CTLL_FC(DW_DMA_FC_D_M2P);
>  
> -		data_width = dw->data_width[dwc->m_master];
> -
>  		for_each_sg(sgl, sg, sg_len, i) {
>  			struct dw_desc	*desc;
>  			u32		len, dlen, mem;
> @@ -827,8 +805,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct
> scatterlist *sgl,
>  			mem = sg_dma_address(sg);
>  			len = sg_dma_len(sg);
>  
> -			mem_width = min_t(unsigned int,
> -					  data_width,
> dwc_fast_ffs(mem | len));
> +			mem_width = __ffs(dw->data_width | mem |
> len);
>  
>  slave_sg_todev_fill_desc:
>  			desc = dwc_desc_get(dwc);
> @@ -874,8 +851,6 @@ slave_sg_todev_fill_desc:
>  		ctllo |= sconfig->device_fc ?
> DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
>  			DWC_CTLL_FC(DW_DMA_FC_D_P2M);
>  
> -		data_width = dw->data_width[dwc->m_master];
> -
>  		for_each_sg(sgl, sg, sg_len, i) {
>  			struct dw_desc	*desc;
>  			u32		len, dlen, mem;
> @@ -883,8 +858,7 @@ slave_sg_todev_fill_desc:
>  			mem = sg_dma_address(sg);
>  			len = sg_dma_len(sg);
>  
> -			mem_width = min_t(unsigned int,
> -					  data_width,
> dwc_fast_ffs(mem | len));
> +			mem_width = __ffs(dw->data_width | mem |
> len);
>  
>  slave_sg_fromdev_fill_desc:
>  			desc = dwc_desc_get(dwc);
> @@ -1531,10 +1505,7 @@ int dw_dma_probe(struct dw_dma_chip *chip,
> struct dw_dma_platform_data *pdata)
>  		/* Get hardware configuration parameters */
>  		pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN
> & 7) + 1;
>  		pdata->nr_masters = (dw_params >>
> DW_PARAMS_NR_MASTER & 3) + 1;
> -		for (i = 0; i < pdata->nr_masters; i++) {
> -			pdata->data_width[i] =
> -				(dw_params >>
> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
> -		}
> +		pdata->data_width = 4 << (dw_params >>
> DW_PARAMS_DATA_WIDTH(0) & 3);
>  		max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
>  
>  		/* Fill platform data with the default values */
> @@ -1556,8 +1527,7 @@ int dw_dma_probe(struct dw_dma_chip *chip,
> struct dw_dma_platform_data *pdata)
>  
>  	/* Get hardware configuration parameters */
>  	dw->nr_masters = pdata->nr_masters;
> -	for (i = 0; i < dw->nr_masters; i++)
> -		dw->data_width[i] = pdata->data_width[i];
> +	dw->data_width = pdata->data_width;
>  
>  	/* Calculate all channel mask before DMA setup */
>  	dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
> diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
> index d3e1abcebd7f..89d0461f5dcc 100644
> --- a/drivers/dma/dw/platform.c
> +++ b/drivers/dma/dw/platform.c
> @@ -102,8 +102,8 @@ dw_dma_parse_dt(struct platform_device *pdev)
>  {
>  	struct device_node *np = pdev->dev.of_node;
>  	struct dw_dma_platform_data *pdata;
> -	u32 tmp, arr[DW_DMA_MAX_NR_MASTERS];
>  	u32 nr_channels;
> +	u32 tmp;
>  
>  	if (!np) {
>  		dev_err(&pdev->dev, "Missing DT data\n");
> @@ -138,10 +138,8 @@ dw_dma_parse_dt(struct platform_device *pdev)
>  		pdata->nr_masters = tmp;
>  	}
>  
> -	if (!of_property_read_u32_array(np, "data_width", arr,
> -				pdata->nr_masters))
> -		for (tmp = 0; tmp < pdata->nr_masters; tmp++)
> -			pdata->data_width[tmp] = arr[tmp];
> +	if (!of_property_read_u32(np, "data-width", &tmp))
> +		pdata->data_width = tmp;
>  
>  	return pdata;
>  }
> diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
> index e4b277565165..87bc97fca084 100644
> --- a/drivers/dma/dw/regs.h
> +++ b/drivers/dma/dw/regs.h
> @@ -285,7 +285,7 @@ struct dw_dma {
>  
>  	/* hardware configuration */
>  	unsigned char		nr_masters;
> -	unsigned char		data_width[DW_DMA_MAX_NR_MASTER
> S];
> +	unsigned char		data_width;
>  };
>  
>  static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma
> *dw)
> diff --git a/include/linux/platform_data/dma-dw.h
> b/include/linux/platform_data/dma-dw.h
> index b881b978e486..4120a3eb71ca 100644
> --- a/include/linux/platform_data/dma-dw.h
> +++ b/include/linux/platform_data/dma-dw.h
> @@ -42,8 +42,7 @@ struct dw_dma_slave {
>   * @chan_priority: Set channel priority increasing from 0 to 7 or 7
> to 0.
>   * @block_size: Maximum block size supported by the controller
>   * @nr_masters: Number of AHB masters supported by the controller
> - * @data_width: Maximum data width supported by hardware per AHB
> master
> - *		(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
> + * @data_width: Maximum data width supported by hardware (in bytes)
>   */
>  struct dw_dma_platform_data {
>  	unsigned int	nr_channels;
> @@ -57,7 +56,7 @@ struct dw_dma_platform_data {
>  	unsigned char	chan_priority;
>  	unsigned short	block_size;
>  	unsigned char	nr_masters;
> -	unsigned char	data_width[DW_DMA_MAX_NR_MASTERS];
> +	unsigned char	data_width;
>  };
>  
>  #endif /* _PLATFORM_DATA_DMA_DW_H */

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 07/15] dmaengine: dw: revisit data_width property

[Rob Herring]

On Sun, Jan 24, 2016 at 07:21:54PM +0000, Mans Rullgard wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> There are several changes are done here:
> 
>  - Convert the property to be in bytes
> 
>    Much more convenient than keeping encoded value.
> 
>  - Use one value for all AHB masters for now
> 
>    It seems in practice we have no controllers where masters have different
>    data bus width, we still might return to distinct values when there is a use
>    case.
> 
>  - Rename data_width to data-width in the device tree bindings.
> 
>  - While here, replace dwc_fast_ffs() by __ffs().
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> This patch changes the DT binding, so it should probably be amended for
> compatibility with old device trees.  I've included it as is since I think
> the change as such is good.

Just because you update the dts files, it doesn't make the change okay. 
I'm fine with the DT change, but the driver would have to support both 
old and new property names. Doesn't really seem worth doing to me.

Rob

Re: [PATCH 07/15] dmaengine: dw: revisit data_width property

[Andy Shevchenko]

On Tue, 2016-01-26 at 15:07 -0600, Rob Herring wrote:
> On Sun, Jan 24, 2016 at 07:21:54PM +0000, Mans Rullgard wrote:

> > This patch changes the DT binding, so it should probably be amended
> > for
> > compatibility with old device trees.  I've included it as is since
> > I think
> > the change as such is good.
> 
> Just because you update the dts files, it doesn't make the change
> okay. 
> I'm fine with the DT change, but the driver would have to support
> both 
> old and new property names.

We will fix this.

>  Doesn't really seem worth doing to me.

The big issue with DT, you know, is hanging around names. This moves
name to be de facto standard for similar in the other drivers.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[PATCH 08/15] dmaengine: dw: define counter variables as unsigned int

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

The code is fixed to satisfy a compiler otherwise we have

drivers/dma/dw/core.c: In function ‘dwc_handle_cyclic’:
drivers/dma/dw/core.c:568: warning: comparison between signed and unsigned
drivers/dma/dw/core.c: In function ‘dw_dma_tasklet’:
drivers/dma/dw/core.c:590: warning: comparison between signed and unsigned
drivers/dma/dw/core.c: In function ‘dw_dma_off’:
drivers/dma/dw/core.c:1103: warning: comparison between signed and unsigned
drivers/dma/dw/core.c: In function ‘dw_dma_cyclic_free’:
drivers/dma/dw/core.c:1469: warning: comparison between signed and unsigned
drivers/dma/dw/core.c: In function ‘dw_dma_probe’:
drivers/dma/dw/core.c:1574: warning: comparison between signed and unsigned

There is no functional change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 28278e4c77ad..0853ade5e636 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -551,7 +551,7 @@ static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 	 */
 	if (unlikely(status_err & dwc->mask) ||
 			unlikely(status_xfer & dwc->mask)) {
-		int i;
+		unsigned int i;
 
 		dev_err(chan2dev(&dwc->chan),
 			"cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
@@ -588,7 +588,7 @@ static void dw_dma_tasklet(unsigned long data)
 	u32 status_block;
 	u32 status_xfer;
 	u32 status_err;
-	int i;
+	unsigned int i;
 
 	status_block = dma_readl(dw, RAW.BLOCK);
 	status_xfer = dma_readl(dw, RAW.XFER);
@@ -1096,7 +1096,7 @@ static void dwc_issue_pending(struct dma_chan *chan)
 
 static void dw_dma_off(struct dw_dma *dw)
 {
-	int i;
+	unsigned int i;
 
 	dma_writel(dw, CFG, 0);
 
@@ -1438,7 +1438,7 @@ void dw_dma_cyclic_free(struct dma_chan *chan)
 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
 	struct dw_dma		*dw = to_dw_dma(dwc->chan.device);
 	struct dw_cyclic_desc	*cdesc = dwc->cdesc;
-	int			i;
+	unsigned int		i;
 	unsigned long		flags;
 
 	dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
@@ -1474,8 +1474,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 	bool			autocfg = false;
 	unsigned int		dw_params;
 	unsigned int		max_blk_size = 0;
+	unsigned int		i;
 	int			err;
-	int			i;
 
 	dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
 	if (!dw)
-- 
2.7.0

[PATCH 09/15] dmaengine: dw: keep entire platform data in struct dw_dma

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Keep the entire platform data in the struct dw_dma.
It makes the driver a bit cleaner.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c                | 31 ++++++++++++++++---------------
 drivers/dma/dw/platform.c            |  4 ++--
 drivers/dma/dw/regs.h                |  5 ++---
 include/linux/platform_data/dma-dw.h |  2 +-
 4 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 0853ade5e636..1644d79a071a 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -710,7 +710,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 
 	dwc->direction = DMA_MEM_TO_MEM;
 
-	src_width = dst_width = __ffs(dw->data_width | src | dest | len);
+	src_width = dst_width = __ffs(dw->pdata->data_width | src | dest | len);
 
 	ctllo = DWC_DEFAULT_CTLLO(chan)
 			| DWC_CTLL_DST_WIDTH(dst_width)
@@ -805,7 +805,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 			mem = sg_dma_address(sg);
 			len = sg_dma_len(sg);
 
-			mem_width = __ffs(dw->data_width | mem | len);
+			mem_width = __ffs(dw->pdata->data_width | mem | len);
 
 slave_sg_todev_fill_desc:
 			desc = dwc_desc_get(dwc);
@@ -858,7 +858,7 @@ slave_sg_todev_fill_desc:
 			mem = sg_dma_address(sg);
 			len = sg_dma_len(sg);
 
-			mem_width = __ffs(dw->data_width | mem | len);
+			mem_width = __ffs(dw->pdata->data_width | mem | len);
 
 slave_sg_fromdev_fill_desc:
 			desc = dwc_desc_get(dwc);
@@ -1473,7 +1473,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 	struct dw_dma		*dw;
 	bool			autocfg = false;
 	unsigned int		dw_params;
-	unsigned int		max_blk_size = 0;
 	unsigned int		i;
 	int			err;
 
@@ -1481,6 +1480,10 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 	if (!dw)
 		return -ENOMEM;
 
+	dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
+	if (!dw->pdata)
+		return -ENOMEM;
+
 	dw->regs = chip->regs;
 	chip->dw = dw;
 
@@ -1496,17 +1499,14 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 			goto err_pdata;
 		}
 
-		pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
-		if (!pdata) {
-			err = -ENOMEM;
-			goto err_pdata;
-		}
+		/* Reassign the platform data pointer */
+		pdata = dw->pdata;
 
 		/* Get hardware configuration parameters */
 		pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
 		pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
 		pdata->data_width = 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(0) & 3);
-		max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
+		pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
 
 		/* Fill platform data with the default values */
 		pdata->is_private = true;
@@ -1516,6 +1516,11 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 	} else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
 		err = -EINVAL;
 		goto err_pdata;
+	} else {
+		memcpy(dw->pdata, pdata, sizeof(*dw->pdata));
+
+		/* Reassign the platform data pointer */
+		pdata = dw->pdata;
 	}
 
 	dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
@@ -1525,10 +1530,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 		goto err_pdata;
 	}
 
-	/* Get hardware configuration parameters */
-	dw->nr_masters = pdata->nr_masters;
-	dw->data_width = pdata->data_width;
-
 	/* Calculate all channel mask before DMA setup */
 	dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
 
@@ -1596,7 +1597,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
 			 * up to 0x0a for 4095.
 			 */
 			dwc->block_size =
-				(4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
+				(4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
 			dwc->nollp =
 				(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
 		} else {
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index 89d0461f5dcc..fcbe57006e59 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -47,8 +47,8 @@ static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
 
 	if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
 		    slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
-		    slave.m_master >= dw->nr_masters ||
-		    slave.p_master >= dw->nr_masters))
+		    slave.m_master >= dw->pdata->nr_masters ||
+		    slave.p_master >= dw->pdata->nr_masters))
 		return NULL;
 
 	dma_cap_zero(cap);
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 87bc97fca084..3e446eccd17c 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -283,9 +283,8 @@ struct dw_dma {
 	u8			all_chan_mask;
 	u8			in_use;
 
-	/* hardware configuration */
-	unsigned char		nr_masters;
-	unsigned char		data_width;
+	/* platform data */
+	struct dw_dma_platform_data	*pdata;
 };
 
 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 4120a3eb71ca..127371722eb3 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -54,7 +54,7 @@ struct dw_dma_platform_data {
 #define CHAN_PRIORITY_ASCENDING		0	/* chan0 highest */
 #define CHAN_PRIORITY_DESCENDING	1	/* chan7 highest */
 	unsigned char	chan_priority;
-	unsigned short	block_size;
+	unsigned int	block_size;
 	unsigned char	nr_masters;
 	unsigned char	data_width;
 };
-- 
2.7.0

[PATCH 10/15] dmaengine: dw: pass platform data via struct dw_dma_chip

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

We pass struct dw_dma_chip to the dw_dma_probe() anyway, thus we may use it to
pass platform data as well.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/ata/sata_dwc_460ex.c          |  2 +-
 drivers/dma/dw/core.c                 |  3 ++-
 drivers/dma/dw/pci.c                  |  3 ++-
 drivers/dma/dw/platform.c             |  3 ++-
 include/linux/dma/dw.h                | 14 ++++++++------
 sound/soc/intel/common/sst-firmware.c |  2 +-
 6 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
index 80bdcabc293f..2cb6f7e04b5c 100644
--- a/drivers/ata/sata_dwc_460ex.c
+++ b/drivers/ata/sata_dwc_460ex.c
@@ -1248,7 +1248,7 @@ static int sata_dwc_probe(struct platform_device *ofdev)
 	hsdev->dma->dev = &ofdev->dev;
 
 	/* Initialize AHB DMAC */
-	err = dw_dma_probe(hsdev->dma, NULL);
+	err = dw_dma_probe(hsdev->dma);
 	if (err)
 		goto error_dma_iomap;
 
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 1644d79a071a..91a6d8b304aa 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1468,8 +1468,9 @@ EXPORT_SYMBOL(dw_dma_cyclic_free);
 
 /*----------------------------------------------------------------------*/
 
-int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
+int dw_dma_probe(struct dw_dma_chip *chip)
 {
+	struct dw_dma_platform_data	*pdata = chip->pdata;
 	struct dw_dma		*dw;
 	bool			autocfg = false;
 	unsigned int		dw_params;
diff --git a/drivers/dma/dw/pci.c b/drivers/dma/dw/pci.c
index 4c30fdd092b3..fc3b954b27da 100644
--- a/drivers/dma/dw/pci.c
+++ b/drivers/dma/dw/pci.c
@@ -49,8 +49,9 @@ static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
 	chip->dev = &pdev->dev;
 	chip->regs = pcim_iomap_table(pdev)[0];
 	chip->irq = pdev->irq;
+	chip->pdata = pdata;
 
-	ret = dw_dma_probe(chip, pdata);
+	ret = dw_dma_probe(chip);
 	if (ret)
 		return ret;
 
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index fcbe57006e59..808bafdd7d48 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -181,6 +181,7 @@ static int dw_probe(struct platform_device *pdev)
 		pdata = dw_dma_parse_dt(pdev);
 
 	chip->dev = dev;
+	chip->pdata = pdata;
 
 	chip->clk = devm_clk_get(chip->dev, "hclk");
 	if (IS_ERR(chip->clk))
@@ -191,7 +192,7 @@ static int dw_probe(struct platform_device *pdev)
 
 	pm_runtime_enable(&pdev->dev);
 
-	err = dw_dma_probe(chip, pdata);
+	err = dw_dma_probe(chip);
 	if (err)
 		goto err_dw_dma_probe;
 
diff --git a/include/linux/dma/dw.h b/include/linux/dma/dw.h
index 71456442ebe3..c9a3914e8a08 100644
--- a/include/linux/dma/dw.h
+++ b/include/linux/dma/dw.h
@@ -27,17 +27,19 @@ struct dw_dma;
  * @regs:		memory mapped I/O space
  * @clk:		hclk clock
  * @dw:			struct dw_dma that is filed by dw_dma_probe()
+ * @pdata:		pointer to platform data
  */
 struct dw_dma_chip {
-	struct device	*dev;
-	int		irq;
-	void __iomem	*regs;
-	struct clk	*clk;
-	struct dw_dma	*dw;
+	struct device			*dev;
+	int				irq;
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct dw_dma			*dw;
+	struct dw_dma_platform_data	*pdata;
 };
 
 /* Export to the platform drivers */
-int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata);
+int dw_dma_probe(struct dw_dma_chip *chip);
 int dw_dma_remove(struct dw_dma_chip *chip);
 
 /* DMA API extensions */
diff --git a/sound/soc/intel/common/sst-firmware.c b/sound/soc/intel/common/sst-firmware.c
index ef4881e7753a..25993527370b 100644
--- a/sound/soc/intel/common/sst-firmware.c
+++ b/sound/soc/intel/common/sst-firmware.c
@@ -203,7 +203,7 @@ static struct dw_dma_chip *dw_probe(struct device *dev, struct resource *mem,
 
 	chip->dev = dev;
 
-	err = dw_dma_probe(chip, NULL);
+	err = dw_dma_probe(chip);
 	if (err)
 		return ERR_PTR(err);
 
-- 
2.7.0

[PATCH 11/15] dmaengine: dw: platform: use field-by-field initialization

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

This is a simple stylish change that allows to use less lines of code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
I'm a little ambivalent on this one.  While the patch is correct as such,
the change means that if struct dw_dma_slave gains new members in future,
these will not be initialised.  This added fragility seems an unnecesary
price to pay for saving one line of code.
---
 drivers/dma/dw/platform.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index 808bafdd7d48..0fd5a49311a2 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -32,14 +32,13 @@ static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
 					struct of_dma *ofdma)
 {
 	struct dw_dma *dw = ofdma->of_dma_data;
-	struct dw_dma_slave slave = {
-		.dma_dev = dw->dma.dev,
-	};
+	struct dw_dma_slave slave;
 	dma_cap_mask_t cap;
 
 	if (dma_spec->args_count != 3)
 		return NULL;
 
+	slave.dma_dev = dw->dma.dev;
 	slave.src_id = dma_spec->args[0];
 	slave.dst_id = dma_spec->args[0];
 	slave.m_master = dma_spec->args[1];
@@ -62,13 +61,13 @@ static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
 static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
 {
 	struct acpi_dma_spec *dma_spec = param;
-	struct dw_dma_slave slave = {
-		.dma_dev = dma_spec->dev,
-		.src_id = dma_spec->slave_id,
-		.dst_id = dma_spec->slave_id,
-		.m_master = 1,
-		.p_master = 0,
-	};
+	struct dw_dma_slave slave;
+
+	slave.dma_dev = dma_spec->dev;
+	slave.src_id = dma_spec->slave_id;
+	slave.dst_id = dma_spec->slave_id;
+	slave.m_master = 1;
+	slave.p_master = 0;
 
 	return dw_dma_filter(chan, &slave);
 }
-- 
2.7.0

Re: [PATCH 11/15] dmaengine: dw: platform: use field-by-field initialization

[Andy Shevchenko]

On Sun, 2016-01-24 at 19:21 +0000, Mans Rullgard wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> This is a simple stylish change that allows to use less lines of
> code.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> I'm a little ambivalent on this one.  While the patch is correct as
> such,
> the change means that if struct dw_dma_slave gains new members in
> future,
> these will not be initialised.  This added fragility seems an
> unnecesary
> price to pay for saving one line of code.

We may use 

 struct dw_dma_slave slave = {0};

if it makes someone happier.

> ---
>  drivers/dma/dw/platform.c | 19 +++++++++----------
>  1 file changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
> index 808bafdd7d48..0fd5a49311a2 100644
> --- a/drivers/dma/dw/platform.c
> +++ b/drivers/dma/dw/platform.c
> @@ -32,14 +32,13 @@ static struct dma_chan *dw_dma_of_xlate(struct
> of_phandle_args *dma_spec,
>  					struct of_dma *ofdma)
>  {
>  	struct dw_dma *dw = ofdma->of_dma_data;
> -	struct dw_dma_slave slave = {
> -		.dma_dev = dw->dma.dev,
> -	};
> +	struct dw_dma_slave slave;
>  	dma_cap_mask_t cap;
>  
>  	if (dma_spec->args_count != 3)
>  		return NULL;
>  
> +	slave.dma_dev = dw->dma.dev;
>  	slave.src_id = dma_spec->args[0];
>  	slave.dst_id = dma_spec->args[0];
>  	slave.m_master = dma_spec->args[1];
> @@ -62,13 +61,13 @@ static struct dma_chan *dw_dma_of_xlate(struct
> of_phandle_args *dma_spec,
>  static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
>  {
>  	struct acpi_dma_spec *dma_spec = param;
> -	struct dw_dma_slave slave = {
> -		.dma_dev = dma_spec->dev,
> -		.src_id = dma_spec->slave_id,
> -		.dst_id = dma_spec->slave_id,
> -		.m_master = 1,
> -		.p_master = 0,
> -	};
> +	struct dw_dma_slave slave;
> +
> +	slave.dma_dev = dma_spec->dev;
> +	slave.src_id = dma_spec->slave_id;
> +	slave.dst_id = dma_spec->slave_id;
> +	slave.m_master = 1;
> +	slave.p_master = 0;
>  
>  	return dw_dma_filter(chan, &slave);
>  }

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[PATCH 12/15] dmaengine: dw: move dwc->paused to dwc->flags

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

We have already dedicated variable for flags, therefore no need to create an
additional storage for that. Convert dwc->paused to use dwc->flags.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 12 +++++-------
 drivers/dma/dw/regs.h |  2 +-
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 91a6d8b304aa..7785f29b8792 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -980,7 +980,7 @@ static int dwc_pause(struct dma_chan *chan)
 	while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 		udelay(2);
 
-	dwc->paused = true;
+	set_bit(DW_DMA_IS_PAUSED, &dwc->flags);
 
 	spin_unlock_irqrestore(&dwc->lock, flags);
 
@@ -993,7 +993,7 @@ static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 
 	channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 
-	dwc->paused = false;
+	clear_bit(DW_DMA_IS_PAUSED, &dwc->flags);
 }
 
 static int dwc_resume(struct dma_chan *chan)
@@ -1001,12 +1001,10 @@ static int dwc_resume(struct dma_chan *chan)
 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
 	unsigned long		flags;
 
-	if (!dwc->paused)
-		return 0;
-
 	spin_lock_irqsave(&dwc->lock, flags);
 
-	dwc_chan_resume(dwc);
+	if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
+		dwc_chan_resume(dwc);
 
 	spin_unlock_irqrestore(&dwc->lock, flags);
 
@@ -1075,7 +1073,7 @@ dwc_tx_status(struct dma_chan *chan,
 	if (ret != DMA_COMPLETE)
 		dma_set_residue(txstate, dwc_get_residue(dwc));
 
-	if (dwc->paused && ret == DMA_IN_PROGRESS)
+	if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS)
 		return DMA_PAUSED;
 
 	return ret;
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 3e446eccd17c..acdd6e820af1 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -216,6 +216,7 @@ enum dw_dma_msize {
 enum dw_dmac_flags {
 	DW_DMA_IS_CYCLIC = 0,
 	DW_DMA_IS_SOFT_LLP = 1,
+	DW_DMA_IS_PAUSED = 2,
 };
 
 struct dw_dma_chan {
@@ -224,7 +225,6 @@ struct dw_dma_chan {
 	u8				mask;
 	u8				priority;
 	enum dma_transfer_direction	direction;
-	bool				paused;
 	bool				initialized;
 
 	/* software emulation of the LLP transfers */
-- 
2.7.0

[PATCH 13/15] dmaengine: dw: move dwc->initialized to dwc->flags

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

We have already dedicated variable for flags, therefore no need to create an
additional storage for that. Covert dwc->initialized to use dwc->flags.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 8 ++++----
 drivers/dma/dw/regs.h | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 7785f29b8792..cd345432fa33 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -138,7 +138,7 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
 	u32 cfghi = DWC_CFGH_FIFO_MODE;
 	u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 
-	if (dwc->initialized == true)
+	if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
 		return;
 
 	if (dws) {
@@ -163,7 +163,7 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
 	channel_set_bit(dw, MASK.BLOCK, dwc->mask);
 	channel_set_bit(dw, MASK.ERROR, dwc->mask);
 
-	dwc->initialized = true;
+	set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
 }
 
 /*----------------------------------------------------------------------*/
@@ -1108,7 +1108,7 @@ static void dw_dma_off(struct dw_dma *dw)
 		cpu_relax();
 
 	for (i = 0; i < dw->dma.chancnt; i++)
-		dw->chan[i].initialized = false;
+		clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags);
 }
 
 static void dw_dma_on(struct dw_dma *dw)
@@ -1201,13 +1201,13 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
 	spin_lock_irqsave(&dwc->lock, flags);
 	list_splice_init(&dwc->free_list, &list);
 	dwc->descs_allocated = 0;
-	dwc->initialized = false;
 
 	/* Disable interrupts */
 	channel_clear_bit(dw, MASK.XFER, dwc->mask);
 	channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
 	channel_clear_bit(dw, MASK.ERROR, dwc->mask);
 
+	clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
 	spin_unlock_irqrestore(&dwc->lock, flags);
 
 	/* Disable controller in case it was a last user */
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index acdd6e820af1..0deb04562c33 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -217,6 +217,7 @@ enum dw_dmac_flags {
 	DW_DMA_IS_CYCLIC = 0,
 	DW_DMA_IS_SOFT_LLP = 1,
 	DW_DMA_IS_PAUSED = 2,
+	DW_DMA_IS_INITIALIZED = 3,
 };
 
 struct dw_dma_chan {
@@ -225,7 +226,6 @@ struct dw_dma_chan {
 	u8				mask;
 	u8				priority;
 	enum dma_transfer_direction	direction;
-	bool				initialized;
 
 	/* software emulation of the LLP transfers */
 	struct list_head	*tx_node_active;
-- 
2.7.0

[PATCH 14/15] dmaengine: dw: move residue to a descriptor

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Residue is a property of any active descriptor. So, any descriptor may be in
different state but residue is a feature of active descriptor. Check if the
asked descriptor is active and return proper residue value for it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 60 ++++++++++++++++++++++++++++++++++-----------------
 drivers/dma/dw/regs.h |  2 +-
 2 files changed, 41 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index cd345432fa33..b6634adf24f9 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -239,7 +239,7 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 
 		dwc_initialize(dwc);
 
-		dwc->residue = first->total_len;
+		first->residue = first->total_len;
 		dwc->tx_node_active = &first->tx_list;
 
 		/* Submit first block */
@@ -370,11 +370,11 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 
 			head = &desc->tx_list;
 			if (active != head) {
-				/* Update desc to reflect last sent one */
-				if (active != head->next)
-					desc = to_dw_desc(active->prev);
-
-				dwc->residue -= desc->len;
+				/* Update residue to reflect last sent descriptor */
+				if (active == head->next)
+					desc->residue -= desc->len;
+				else
+					desc->residue -= to_dw_desc(active->prev)->len;
 
 				child = to_dw_desc(active);
 
@@ -389,8 +389,6 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 			clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 		}
 
-		dwc->residue = 0;
-
 		spin_unlock_irqrestore(&dwc->lock, flags);
 
 		dwc_complete_all(dw, dwc);
@@ -398,7 +396,6 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 	}
 
 	if (list_empty(&dwc->active_list)) {
-		dwc->residue = 0;
 		spin_unlock_irqrestore(&dwc->lock, flags);
 		return;
 	}
@@ -413,7 +410,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 
 	list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 		/* Initial residue value */
-		dwc->residue = desc->total_len;
+		desc->residue = desc->total_len;
 
 		/* Check first descriptors addr */
 		if (desc->txd.phys == DWC_LLP_LOC(llp)) {
@@ -424,20 +421,20 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 		/* Check first descriptors llp */
 		if (lli_read(desc, llp) == llp) {
 			/* This one is currently in progress */
-			dwc->residue -= dwc_get_sent(dwc);
+			desc->residue -= dwc_get_sent(dwc);
 			spin_unlock_irqrestore(&dwc->lock, flags);
 			return;
 		}
 
-		dwc->residue -= desc->len;
+		desc->residue -= desc->len;
 		list_for_each_entry(child, &desc->tx_list, desc_node) {
 			if (lli_read(child, llp) == llp) {
 				/* Currently in progress */
-				dwc->residue -= dwc_get_sent(dwc);
+				desc->residue -= dwc_get_sent(dwc);
 				spin_unlock_irqrestore(&dwc->lock, flags);
 				return;
 			}
-			dwc->residue -= child->len;
+			desc->residue -= child->len;
 		}
 
 		/*
@@ -1040,16 +1037,37 @@ static int dwc_terminate_all(struct dma_chan *chan)
 	return 0;
 }
 
-static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
+static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c)
 {
+	struct dw_desc *desc;
+
+	list_for_each_entry(desc, &dwc->active_list, desc_node)
+		if (desc->txd.cookie == c)
+			return desc;
+
+	return NULL;
+}
+
+static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie)
+{
+	struct dw_desc *desc;
 	unsigned long flags;
 	u32 residue;
 
 	spin_lock_irqsave(&dwc->lock, flags);
 
-	residue = dwc->residue;
-	if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
-		residue -= dwc_get_sent(dwc);
+	desc = dwc_find_desc(dwc, cookie);
+	if (desc) {
+		if (desc == dwc_first_active(dwc)) {
+			residue = desc->residue;
+			if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
+				residue -= dwc_get_sent(dwc);
+		} else {
+			residue = desc->total_len;
+		}
+	} else {
+		residue = 0;
+	}
 
 	spin_unlock_irqrestore(&dwc->lock, flags);
 	return residue;
@@ -1070,8 +1088,10 @@ dwc_tx_status(struct dma_chan *chan,
 	dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 
 	ret = dma_cookie_status(chan, cookie, txstate);
-	if (ret != DMA_COMPLETE)
-		dma_set_residue(txstate, dwc_get_residue(dwc));
+	if (ret == DMA_COMPLETE)
+		return ret;
+
+	dma_set_residue(txstate, dwc_get_residue(dwc, cookie));
 
 	if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS)
 		return DMA_PAUSED;
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 0deb04562c33..180a0cc00e41 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -237,7 +237,6 @@ struct dw_dma_chan {
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
-	u32			residue;
 	struct dw_cyclic_desc	*cdesc;
 
 	unsigned int		descs_allocated;
@@ -351,6 +350,7 @@ struct dw_desc {
 	struct dma_async_tx_descriptor	txd;
 	size_t				len;
 	size_t				total_len;
+	u32				residue;
 };
 
 #define to_dw_desc(h)	list_entry(h, struct dw_desc, desc_node)
-- 
2.7.0

[PATCH 15/15] dmaengine: dw: set cdesc to NULL when free cyclic transfers

[Mans Rullgard]

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

To be sure we have the cyclic transfers already gone we set cdesc to NULL. It
will prevent the double free.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/dma/dw/core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index b6634adf24f9..5606deb7f060 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1480,6 +1480,8 @@ void dw_dma_cyclic_free(struct dma_chan *chan)
 	kfree(cdesc->desc);
 	kfree(cdesc);
 
+	dwc->cdesc = NULL;
+
 	clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
 }
 EXPORT_SYMBOL(dw_dma_cyclic_free);
-- 
2.7.0

Re: [PATCH 00/15] dmaengine: dw: various fixes and cleanups

[Andy Shevchenko]

On Sun, 2016-01-24 at 19:21 +0000, Mans Rullgard wrote:
> This patch series contains a number of mostly minor fixes and
> cleanups
> for the DW DMA driver.  A couple of them affect the DT binding so
> these
> may need to be updated to maintain compatibility.  The rest should be
> relatively straight-forward.
> 
> Andy's branch had two additional patches which I have ommitted here
> since
> one, "dmaengine: dw: clear soft LLP flag in case of error", doesn't
> look
> correct and the other, "dmaengine: dw: split dwc_dostart() helper to
> two",
> depends on the first.

Thanks for keeping this up!

So, for all your patches in the series

Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> Andy Shevchenko (11):
>   dmaengine: dw: rename masters to reflect actual topology
>   dmaengine: dw: substitute dma_read_byaddr by dma_readl_native
>   dmaengine: dw: revisit data_width property
>   dmaengine: dw: define counter variables as unsigned int
>   dmaengine: dw: keep entire platform data in struct dw_dma
>   dmaengine: dw: pass platform data via struct dw_dma_chip
>   dmaengine: dw: platform: use field-by-field initialization
>   dmaengine: dw: move dwc->paused to dwc->flags
>   dmaengine: dw: move dwc->initialized to dwc->flags
>   dmaengine: dw: move residue to a descriptor
>   dmaengine: dw: set cdesc to NULL when free cyclic transfers
> 
> Mans Rullgard (4):
>   dmaengine: dw: fix byte order of hw descriptor fields
>   dmaengine: dw: clear LLP_[SD]_EN bits in last descriptor of a chain
>   dmaengine: dw: set src and dst master select according to xfer
>     direction
>   dmaengine: dw: set LMS field in descriptors
> 
>  Documentation/devicetree/bindings/dma/snps-dma.txt |   9 +-
>  arch/arc/boot/dts/abilis_tb10x.dtsi                |   2 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |   4 +-
>  arch/avr32/mach-at32ap/at32ap700x.c                |  16 +-
>  drivers/ata/sata_dwc_460ex.c                       |   6 +-
>  drivers/dma/dw/core.c                              | 295 ++++++++++-
> ----------
>  drivers/dma/dw/pci.c                               |   3 +-
>  drivers/dma/dw/platform.c                          |  38 ++-
>  drivers/dma/dw/regs.h                              |  55 ++--
>  drivers/spi/spi-pxa2xx-pci.c                       |   8 +-
>  drivers/tty/serial/8250/8250_pci.c                 |   8 +-
>  include/linux/dma/dw.h                             |  14 +-
>  include/linux/platform_data/dma-dw.h               |  15 +-
>  sound/soc/intel/common/sst-firmware.c              |   2 +-
>  14 files changed, 241 insertions(+), 234 deletions(-)
> 

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 00/15] dmaengine: dw: various fixes and cleanups

[Vinod Koul]

On Sun, Jan 24, 2016 at 07:21:47PM +0000, Mans Rullgard wrote:
> This patch series contains a number of mostly minor fixes and cleanups
> for the DW DMA driver.  A couple of them affect the DT binding so these
> may need to be updated to maintain compatibility.  The rest should be
> relatively straight-forward.
> 
> Andy's branch had two additional patches which I have ommitted here since
> one, "dmaengine: dw: clear soft LLP flag in case of error", doesn't look
> correct and the other, "dmaengine: dw: split dwc_dostart() helper to two",
> depends on the first.
> 
> Andy Shevchenko (11):
>   dmaengine: dw: rename masters to reflect actual topology
>   dmaengine: dw: substitute dma_read_byaddr by dma_readl_native
>   dmaengine: dw: revisit data_width property
>   dmaengine: dw: define counter variables as unsigned int
>   dmaengine: dw: keep entire platform data in struct dw_dma
>   dmaengine: dw: pass platform data via struct dw_dma_chip
>   dmaengine: dw: platform: use field-by-field initialization
>   dmaengine: dw: move dwc->paused to dwc->flags
>   dmaengine: dw: move dwc->initialized to dwc->flags
>   dmaengine: dw: move residue to a descriptor
>   dmaengine: dw: set cdesc to NULL when free cyclic transfers
> 
> Mans Rullgard (4):
>   dmaengine: dw: fix byte order of hw descriptor fields
>   dmaengine: dw: clear LLP_[SD]_EN bits in last descriptor of a chain
>   dmaengine: dw: set src and dst master select according to xfer
>     direction
>   dmaengine: dw: set LMS field in descriptors
> 
>  Documentation/devicetree/bindings/dma/snps-dma.txt |   9 +-
>  arch/arc/boot/dts/abilis_tb10x.dtsi                |   2 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |   4 +-
>  arch/avr32/mach-at32ap/at32ap700x.c                |  16 +-
>  drivers/ata/sata_dwc_460ex.c                       |   6 +-
>  drivers/dma/dw/core.c                              | 295 ++++++++++-----------
>  drivers/dma/dw/pci.c                               |   3 +-
>  drivers/dma/dw/platform.c                          |  38 ++-
>  drivers/dma/dw/regs.h                              |  55 ++--
>  drivers/spi/spi-pxa2xx-pci.c                       |   8 +-
>  drivers/tty/serial/8250/8250_pci.c                 |   8 +-
>  include/linux/dma/dw.h                             |  14 +-
>  include/linux/platform_data/dma-dw.h               |  15 +-
>  sound/soc/intel/common/sst-firmware.c              |   2 +-
>  14 files changed, 241 insertions(+), 234 deletions(-)

Your patch title are also misleading. Only dmaengine code should have tag
"dmaengine: dw:" rest should have their own subsystem tags. This will help
folks review their changes faster

-- 
~Vinod