[PATCH v2 05/15] dmaengine: dw: set LMS field in descriptors

Andy Shevchenko
2016-02-22T16:08:25Z

From: Mans Rullgard <mans@mansr.com>

The LMS field indicates from which master the descriptor is to be
read. This patch assumes this is always the same as the memory
side in a peripheral transfer which is true for all known systems.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/dma/dw/core.c | 19 +++++++++----------
drivers/dma/dw/regs.h | 4 ++++
2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 67e8618..90299fe 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -264,7 +264,7 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)

dwc_initialize(dwc);

- channel_writel(dwc, LLP, first->txd.phys);
+ channel_writel(dwc, LLP, first->txd.phys | DWC_LLP_LMS(dwc->m_master));
channel_writel(dwc, CTL_LO,
DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
channel_writel(dwc, CTL_HI, 0);
@@ -430,7 +430,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
dwc->residue = desc->total_len;

/* Check first descriptors addr */
- if (desc->txd.phys == llp) {
+ if (desc->txd.phys == DWC_LLP_LOC(llp)) {
spin_unlock_irqrestore(&dwc->lock, flags);
return;
}
@@ -755,7 +755,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
if (!first) {
first = desc;
} else {
- lli_write(prev, llp, desc->txd.phys);
+ lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));
list_add_tail(&desc->desc_node, &first->tx_list);
}
prev = desc;
@@ -852,7 +852,7 @@ slave_sg_todev_fill_desc:
if (!first) {
first = desc;
} else {
- lli_write(prev, llp, desc->txd.phys);
+ lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));
list_add_tail(&desc->desc_node, &first->tx_list);
}
prev = desc;
@@ -907,7 +907,7 @@ slave_sg_fromdev_fill_desc:
if (!first) {
first = desc;
} else {
- lli_write(prev, llp, desc->txd.phys);
+ lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));
list_add_tail(&desc->desc_node, &first->tx_list);
}
prev = desc;
@@ -1432,13 +1432,13 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
cdesc->desc[i] = desc;

if (last)
- lli_write(last, llp, desc->txd.phys);
+ lli_write(last, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master));

last = desc;
}

/* Let's make a cyclic list */
- lli_write(last, llp, cdesc->desc[0]->txd.phys);
+ lli_write(last, llp, cdesc->desc[0]->txd.phys | DWC_LLP_LMS(dwc->m_master));

dev_dbg(chan2dev(&dwc->chan),
"cyclic prepared buf %pad len %zu period %zu periods %d\n",
@@ -1640,9 +1640,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
dwc->block_size = pdata->block_size;

/* Check if channel supports multi block transfer */
- channel_writel(dwc, LLP, 0xfffffffc);
- dwc->nollp =
- (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
+ channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));
+ dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
channel_writel(dwc, LLP, 0);
}
}
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 6571100..59d6cec 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -143,6 +143,10 @@ enum dw_dma_msize {
DW_DMA_MSIZE_256,
};

+/* Bitfields in LLP */
+#define DWC_LLP_LMS(x) ((x) & 3) /* list master select */
+#define DWC_LLP_LOC(x) ((x) & ~3) /* next lli */
+
/* Bitfields in CTL_LO */
#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
--
2.7.0