From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757916AbcDEKtO (ORCPT ); Tue, 5 Apr 2016 06:49:14 -0400 Received: from mga02.intel.com ([134.134.136.20]:35349 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751513AbcDEKtM (ORCPT ); Tue, 5 Apr 2016 06:49:12 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,443,1455004800"; d="scan'208";a="948338354" Message-ID: <1459853407.12843.7.camel@linux.intel.com> Subject: Re: [PATCH v4] serial: 8250_dw: fix wrong logic in dw8250_check_lcr() From: Andy Shevchenko To: Kefeng Wang , Noam Camus , Greg Kroah-Hartman Cc: Heikki Krogerus , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, guohanjun@huawei.com, xuwei5@hisilicon.com Date: Tue, 05 Apr 2016 13:50:07 +0300 In-Reply-To: <1459835585-25751-1-git-send-email-wangkefeng.wang@huawei.com> References: <1459827166-13861-1-git-send-email-wangkefeng.wang@huawei.com> <1459835585-25751-1-git-send-email-wangkefeng.wang@huawei.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.5.1-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2016-04-05 at 13:53 +0800, Kefeng Wang wrote: > Commit cdcea058e510 ("serial: 8250_dw: Avoid serial_outx code > duplicate > with new dw8250_check_lcr()") introduce a wrong logic when write val > to > LCR reg. When CONFIG_64BIT enabled, __raw_writeq is used > unconditionally. > > The __raw_readq/__raw_writeq is introduced by commit bca2092d7897 > ("serial: > 8250_dw: Use 64-bit access for OCTEON.") for OCTEON, so for > !PORT_OCTEON, > we better to use coincident write func. > > Fixes: cdcea058e510("serial: 8250_dw: Avoid serial_outx code > duplicate with new dw8250_check_lcr()") > Signed-off-by: Kefeng Wang > --- > > Changes since v3: > - Add patch change log, suggested by Greg Kroah-Hartman. > Changes since v2: > - Add #ifdef CONFIG_64BIT back, ensure it can be built under Oh, true. Since it's a native IO we can't use writeq() helper from io- 64-nonatomic-*.  > configuration lacking readq/writeq. > Changes since v1: > - Repace '#ifdef CONFIG_64BIT' with IS_ENABLED(CONFIG_64BIT). > - Enrich patch log, and add Fixes tag. >    > >  drivers/tty/serial/8250/8250_dw.c | 7 ++++--- >  1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/tty/serial/8250/8250_dw.c > b/drivers/tty/serial/8250/8250_dw.c > index a3fb95d..47d1f3e 100644 > --- a/drivers/tty/serial/8250/8250_dw.c > +++ b/drivers/tty/serial/8250/8250_dw.c > @@ -104,15 +104,16 @@ static void dw8250_check_lcr(struct uart_port > *p, int value) >   dw8250_force_idle(p); >   >  #ifdef CONFIG_64BIT > - __raw_writeq(value & 0xff, offset); > -#else > + if (p->type == PORT_OCTEON) > + __raw_writeq(value & 0xff, offset); > + else > +#endif >   if (p->iotype == UPIO_MEM32) >   writel(value, offset); >   else if (p->iotype == UPIO_MEM32BE) >   iowrite32be(value, offset); >   else >   writeb(value, offset); > -#endif So, this changes logic to write the value on any 64 platform, using different (non-64-bit) accessors, so, the case to fix is actually "64BIT && !PORT_OCTEON". Perhaps commit message should be amended to point that clearly. >   } >   /* >    * FIXME: this deadlocks if port->lock is already held -- Andy Shevchenko Intel Finland Oy