From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Viresh Kumar <vireshk@kernel.org>,
Vinod Koul <vinod.koul@intel.com>,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>, Mark Brown <broonie@kernel.org>,
Vineet Gupta <vgupta@synopsys.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: [PATCH v4 4/4] dmaengine: dw: override LLP support if asked in platform data
Date: Thu, 21 Apr 2016 18:03:14 +0300 [thread overview]
Message-ID: <1461250994-62090-5-git-send-email-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <1461250994-62090-1-git-send-email-andriy.shevchenko@linux.intel.com>
There is at least one known device, i.e. UART on Intel Galileo, that works
unreliably in case of use of multi block transfer support in DMA mode.
Override autodetection by user provided data.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/dma/dw/core.c | 10 +++++++---
include/linux/platform_data/dma-dw.h | 2 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 9c7bc7a..f66d104 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1571,9 +1571,13 @@ int dw_dma_probe(struct dw_dma_chip *chip)
dwc->block_size = pdata->block_size;
/* Check if channel supports multi block transfer */
- channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));
- dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
- channel_writel(dwc, LLP, 0);
+ if (pdata->is_nollp) {
+ dwc->nollp = pdata->is_nollp;
+ } else {
+ channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));
+ dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
+ channel_writel(dwc, LLP, 0);
+ }
}
}
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 192f3a2..ec7f7d3 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -40,6 +40,7 @@ struct dw_dma_slave {
* @is_private: The device channels should be marked as private and not for
* by the general purpose DMA channel allocator.
* @is_memcpy: The device channels do support memory-to-memory transfers.
+ * @is_nollp: The device channels does not support multi block transfers.
* @chan_allocation_order: Allocate channels starting from 0 or 7
* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
* @block_size: Maximum block size supported by the controller
@@ -51,6 +52,7 @@ struct dw_dma_platform_data {
unsigned int nr_channels;
bool is_private;
bool is_memcpy;
+ bool is_nollp;
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
unsigned char chan_allocation_order;
--
2.8.0.rc3
next prev parent reply other threads:[~2016-04-21 15:04 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-21 15:03 [PATCH v4 0/4] Fixes / cleanups in dw_dmac (affects on few subsystems) Andy Shevchenko
2016-04-21 15:03 ` [PATCH v4 1/4] dmaengine: dw: keep copy of custom slave config in dwc Andy Shevchenko
2016-04-21 15:03 ` [PATCH v4 2/4] dmaengine: dw: provide probe(), remove() stubs for users Andy Shevchenko
2016-04-21 15:03 ` [PATCH v4 3/4] dmaengine: dw: set polarity of handshake interface Andy Shevchenko
2016-04-21 15:03 ` Andy Shevchenko [this message]
2016-04-21 15:06 ` [PATCH v4 0/4] Fixes / cleanups in dw_dmac (affects on few subsystems) Andy Shevchenko
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