From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932484AbcEKXKv (ORCPT ); Wed, 11 May 2016 19:10:51 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:34418 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751788AbcEKXCo (ORCPT ); Wed, 11 May 2016 19:02:44 -0400 From: David Carrillo-Cisneros To: Peter Zijlstra , Alexander Shishkin , Arnaldo Carvalho de Melo , Ingo Molnar Cc: Vikas Shivappa , Matt Fleming , Tony Luck , Stephane Eranian , Paul Turner , David Carrillo-Cisneros , x86@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/32] perf/x86/intel/cqm: software cache for MSR_IA32_PQR_ASSOC Date: Wed, 11 May 2016 16:02:02 -0700 Message-Id: <1463007752-116802-3-git-send-email-davidcc@google.com> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1463007752-116802-1-git-send-email-davidcc@google.com> References: <1463007752-116802-1-git-send-email-davidcc@google.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The msr MSR_IA32_PQR_ASSOC is shared by CQM and the upcoming CAT. Since writes to this msr are slow (more than 1000 cycles) and mostly occur in context switch, this patch introduces a software cache that avoids wrsmr that wont change the msr's value. Reviewed-by: Stephane Eranian Signed-off-by: David Carrillo-Cisneros --- arch/x86/include/asm/pqr_common.h | 44 +++++++++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/pqr_common.c | 8 +++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/x86/include/asm/pqr_common.h create mode 100644 arch/x86/kernel/cpu/pqr_common.c diff --git a/arch/x86/include/asm/pqr_common.h b/arch/x86/include/asm/pqr_common.h new file mode 100644 index 0000000..854febe --- /dev/null +++ b/arch/x86/include/asm/pqr_common.h @@ -0,0 +1,44 @@ +#ifndef _X86_PQR_COMMON_H_ +#define _X86_PQR_COMMON_H_ + +#if defined(CONFIG_INTEL_RDT) + +#include +#include +#include + +#define MSR_IA32_PQR_ASSOC 0x0c8f + +#define INVALID_RMID (-1) + +/** + * struct intel_pqr_state - State cache for the PQR MSR + * @rmid: The cached Resource Monitoring ID + * @closid: The cached Class Of Service ID + * + * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the + * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always + * contains both parts, so we need to cache them. + * + * The cache also helps to avoid pointless updates if the value does + * not change. + */ +struct intel_pqr_state { + u32 rmid; + u32 closid; +}; + +DECLARE_PER_CPU(struct intel_pqr_state, pqr_state); + +static inline void pqr_update_rmid(u32 rmid) +{ + struct intel_pqr_state *state = this_cpu_ptr(&pqr_state); + + if (state->rmid == rmid) + return; + state->rmid = rmid; + wrmsr(MSR_IA32_PQR_ASSOC, rmid, state->closid); +} + +#endif +#endif diff --git a/arch/x86/kernel/cpu/pqr_common.c b/arch/x86/kernel/cpu/pqr_common.c new file mode 100644 index 0000000..dc6debc --- /dev/null +++ b/arch/x86/kernel/cpu/pqr_common.c @@ -0,0 +1,8 @@ +#include + +/* + * The cached intel_pqr_state is strictly per CPU and can never be + * updated from a remote CPU. Functions that modify pqr_state + * must ensure interruptions are properly handled. + */ +DEFINE_PER_CPU(struct intel_pqr_state, pqr_state); -- 2.8.0.rc3.226.g39d4020