From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932687AbcFBM4A (ORCPT ); Thu, 2 Jun 2016 08:56:00 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:41898 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932408AbcFBMz6 (ORCPT ); Thu, 2 Jun 2016 08:55:58 -0400 Message-ID: <1464872124.3307.22.camel@pengutronix.de> Subject: Re: [PATCH 2/5] arm/dts/imx6q-b850v3: Configure IPU assignment order From: Philipp Zabel To: Peter Senna Tschudin Cc: airlied@linux.ie, akpm@linux-foundation.org, davem@davemloft.net, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, enric.balletbo@collabora.com, galak@codeaurora.org, gregkh@linuxfoundation.org, heiko@sntech.de, ijc+devicetree@hellion.org.uk, jslaby@suse.cz, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk, linux-kernel@vger.kernel.org, linux@roeck-us.net, mark.rutland@arm.com, martin.donnelly@ge.com, martyn.welch@collabora.co.uk, mchehab@osg.samsung.com, pawel.moll@arm.com, rmk+kernel@armlinux.org.uk, robh+dt@kernel.org, shawnguo@kernel.org, tiwai@suse.com, treding@nvidia.com, ykk@rock-chips.com Date: Thu, 02 Jun 2016 14:55:24 +0200 In-Reply-To: <1464626385-19253-3-git-send-email-peter.senna@collabora.com> References: <1464626385-19253-1-git-send-email-peter.senna@collabora.com> <1464626385-19253-3-git-send-email-peter.senna@collabora.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Montag, den 30.05.2016, 18:39 +0200 schrieb Peter Senna Tschudin: > Configure the IPU assignment order to assign one IPU per external > display. A single IPU can drive multiple external displays but there are > resolution restrictions. After this patch the GPU is capalbe of driving two > Full-HD monitors. It's also capable to do it before this patch, if you use the first and third crtc. You are just reordering the crtcs. Unfortunately the IPU has combined limitations across multiple crtcs in one IPU, which currently can't be communicated to userspace. regards Philipp