From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752570AbcFNPqQ (ORCPT ); Tue, 14 Jun 2016 11:46:16 -0400 Received: from mga09.intel.com ([134.134.136.24]:43550 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751913AbcFNPqL (ORCPT ); Tue, 14 Jun 2016 11:46:11 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,471,1459839600"; d="scan'208";a="987283535" Message-ID: <1465919250.30123.74.camel@linux.intel.com> Subject: Re: [PATCH v1 1/1] x86/platform/intel-mid: Make vertical indentation consistent From: Andy Shevchenko To: Ingo Molnar Cc: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org Date: Tue, 14 Jun 2016 18:47:30 +0300 In-Reply-To: <20160614153324.GC28601@gmail.com> References: <1465914790-92911-1-git-send-email-andriy.shevchenko@linux.intel.com> <20160614153324.GC28601@gmail.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.20.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2016-06-14 at 17:33 +0200, Ingo Molnar wrote: > How about this as well, on top of yours? Looks definitely good to me! Thanks! > > =================> > > Make vertical alignment really consistent across this header, plus fix > various  > uglies like unnecessary parentheses and C comments from definition > values. > > Cc: Linus Torvalds > Cc: Peter Zijlstra > Cc: Thomas Gleixner > Signed-off-by: Ingo Molnar > --- >  arch/x86/include/asm/intel-mid.h |   45 ++++++++++++++++++++--------- > ---------- >  1 file changed, 24 insertions(+), 21 deletions(-) > > Index: tip/arch/x86/include/asm/intel-mid.h > =================================================================== > --- tip.orig/arch/x86/include/asm/intel-mid.h > +++ tip/arch/x86/include/asm/intel-mid.h > @@ -74,7 +74,7 @@ struct intel_mid_ops { >   [cpuid] = get_##cpuname##_ops >   >  /* Maximum number of CPU ops */ > -#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) > +#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void > *)) >   >  /* >   * For every new cpu addition, a weak get__ops() function > needs be > @@ -100,8 +100,8 @@ static inline bool intel_mid_has_msic(vo >   >  #else /* !CONFIG_X86_INTEL_MID */ >   > -#define intel_mid_identify_cpu() (0) > -#define intel_mid_has_msic() (0) > +#define intel_mid_identify_cpu() 0 > +#define intel_mid_has_msic() 0 >   >  #endif /* !CONFIG_X86_INTEL_MID */ >   > @@ -117,35 +117,38 @@ extern enum intel_mid_timer_options inte >   * Penwell uses spread spectrum clock, so the freq number is not > exactly >   * the same as reported by MSR based on SDM. >   */ > -#define FSB_FREQ_83SKU 83200 > -#define FSB_FREQ_100SKU 99840 > -#define FSB_FREQ_133SKU 133000 > - > -#define FSB_FREQ_167SKU 167000 > -#define FSB_FREQ_200SKU 200000 > -#define FSB_FREQ_267SKU 267000 > -#define FSB_FREQ_333SKU 333000 > -#define FSB_FREQ_400SKU 400000 > +#define FSB_FREQ_83SKU 83200 > +#define FSB_FREQ_100SKU 99840 > +#define FSB_FREQ_133SKU 133000 > + > +#define FSB_FREQ_167SKU 167000 > +#define FSB_FREQ_200SKU 200000 > +#define FSB_FREQ_267SKU 267000 > +#define FSB_FREQ_333SKU 333000 > +#define FSB_FREQ_400SKU 400000 >   >  /* Bus Select SoC Fuse value */ > -#define BSEL_SOC_FUSE_MASK 0x7 > -#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ > -#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ > -#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ > +#define BSEL_SOC_FUSE_MASK 0x7 > +/* FSB 133MHz: */ > +#define BSEL_SOC_FUSE_001 0x1 > +/* FSB 100MHz: */ > +#define BSEL_SOC_FUSE_101 0x5 > +/* FSB 83MHz: */ > +#define BSEL_SOC_FUSE_111 0x7 >   > -#define SFI_MTMR_MAX_NUM 8 > -#define SFI_MRTC_MAX 8 > +#define SFI_MTMR_MAX_NUM 8 > +#define SFI_MRTC_MAX 8 >   >  extern void intel_scu_devices_create(void); >  extern void intel_scu_devices_destroy(void); >   >  /* VRTC timer */ > -#define MRST_VRTC_MAP_SZ (1024) > -/* #define MRST_VRTC_PGOFFSET (0xc00) */ > +#define MRST_VRTC_MAP_SZ 1024 > +/* #define MRST_VRTC_PGOFFSET 0xc00 */ >   >  extern void intel_mid_rtc_init(void); >   >  /* the offset for the mapping of global gpio pin to irq */ > -#define INTEL_MID_IRQ_OFFSET 0x100 > +#define INTEL_MID_IRQ_OFFSET 0x100 >   >  #endif /* _ASM_X86_INTEL_MID_H */ -- Andy Shevchenko Intel Finland Oy