From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752038AbcFUKgM (ORCPT ); Tue, 21 Jun 2016 06:36:12 -0400 Received: from mga03.intel.com ([134.134.136.65]:19000 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751756AbcFUKgC (ORCPT ); Tue, 21 Jun 2016 06:36:02 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,503,1459839600"; d="scan'208";a="992035850" Message-ID: <1466505306.30123.203.camel@linux.intel.com> Subject: Re: [PATCH net-next 01/19] net: hns: bug fix of ge reset sequence From: Andy Shevchenko To: Yisen Zhuang , davem@davemloft.net, salil.mehta@huawei.com, yankejian@huawei.com Cc: liguozhu@huawei.com, huangdaode@hisilicon.com, arnd@arndb.de, andrew@lunn.ch, geliangtang@163.com, ivecera@redhat.com, fengguang.wu@intel.com, charles.chenxin@huawei.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Date: Tue, 21 Jun 2016 13:35:06 +0300 In-Reply-To: <1466481399-70080-2-git-send-email-Yisen.Zhuang@huawei.com> References: <1466481399-70080-1-git-send-email-Yisen.Zhuang@huawei.com> <1466481399-70080-2-git-send-email-Yisen.Zhuang@huawei.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.20.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2016-06-21 at 11:56 +0800, Yisen Zhuang wrote: > From: Qianqian Xie > > The bit fileds of PPE reset register are different between HNS v1 and > HNS v2, but the current procedure just only match HNS v1. Here is a > patch to fix it. > > Signed-off-by: Kejian Yan > Signed-off-by: Qianqian Xie > Signed-off-by: Yisen Zhuang > --- >  drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 6 +++++- >  1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c > b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c > index 96cb628..09e60d6 100644 > --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c > +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c > @@ -271,7 +271,11 @@ static void hns_dsaf_ge_srst_by_port(struct > dsaf_device *dsaf_dev, u32 port, >   } >   } else { >   reg_val_1 = 0x15540 << dsaf_dev->reset_offset; > - reg_val_2 = 0x100 << dsaf_dev->reset_offset; > + > + if (AE_IS_VER1(dsaf_dev->dsaf_ver)) > + reg_val_2 = 0x100 << dsaf_dev->reset_offset; > + else > + reg_val_2 = 0x40 << dsaf_dev->reset_offset; reg_val_1 = 0x15540; reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40; reg_val_1 <<= dsaf_dev->reset_offset; reg_val_2 <<= dsaf_dev- >reset_offset; >   >   if (!dereset) { >   dsaf_write_sub(dsaf_dev, > DSAF_SUB_SC_GE_RESET_REQ1_REG, -- Andy Shevchenko Intel Finland Oy