From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752669AbcGALil (ORCPT ); Fri, 1 Jul 2016 07:38:41 -0400 Received: from mail-sn1nam02on0047.outbound.protection.outlook.com ([104.47.36.47]:31264 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751994AbcGALiT (ORCPT ); Fri, 1 Jul 2016 07:38:19 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Kedareswara rao Appana To: , , , , , , , , , , , , , CC: , , , Subject: [PATCH v12 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Date: Fri, 1 Jul 2016 17:07:05 +0530 Message-ID: <1467373026-27768-1-git-send-email-appanad@xilinx.com> X-Mailer: git-send-email 2.1.1 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22424.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(438002)(189002)(199003)(8676002)(50466002)(52956003)(92566002)(86362001)(48376002)(7846002)(2201001)(356003)(305945005)(106466001)(229853001)(19580395003)(19580405001)(81166006)(586003)(103686003)(36386004)(4326007)(50226002)(33646002)(81156014)(63266004)(46386002)(47776003)(8936002)(5001770100001)(42186005)(2906002)(90966002)(50986999)(5003940100001)(45336002)(87936001)(4001450100002)(36756003)(189998001)(107986001)(921003)(2101003)(83996005)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT084;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;MX:1;A:1;CAT:NONE;LANG:en;CAT:NONE; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 9215ae96-49cc-43bc-a975-08d3a1a4101b X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT084; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13023025)(13024025)(13015025)(8121501046)(5005006)(13017025)(13018025)(3002001)(10201501046)(6055026);SRVR:CY1NAM02HT084;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT084; X-Forefront-PRVS: 0990C54589 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2016 11:37:19.7109 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT084 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Device-tree binding documentation for Xilinx zynqmp dma engine used in Zynq UltraScale+ MPSoC. Acked-by: Rob Herring Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Kedareswara rao Appana --- Changes in v12: - None. Changes in v11: - None. Changes in v10: - Added Rob Acked-by in the commit message. Changs in v9: - Removed include sg runtime configuration parameter from the binding doc as suggested by Lars. Changes in v8: - Removed all the software runtime configuration parameters from the binding doc as suggested by the Lars. Changes in v7: - None. Changes in v6: - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties from the binding doc as it allow broken combinations when dma-coherent is set as suggested by Rob. - Fixed minor comments given by Rob related coding(lower case DT node name). Changes in v5: - Use dma-coherent flag for coherent transfers as suggested by rob. - Removed unnecessary properties from binding doc as suggested by Rob. Changes in v4: - None Changes in v3: - None Changes in v2: - None. .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 27 ++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 0000000..a784cdd --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,27 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible : Should be "xlnx,zynqmp-dma-1.0" +- reg : Memory map for gdma/adma module access. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain DMA channel interrupt. +- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 +- clock-names : List of input clocks "clk_main", "clk_apb" + (see clock bindings for details) + +Optional properties: +- dma-coherent : Present if dma operations are coherent. + +Example: +++++++++ +fpd_dma_chan1: dma@fd500000 { + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xFD500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 117 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + dma-coherent; +}; -- 1.7.1