From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754123AbcGFLEC (ORCPT ); Wed, 6 Jul 2016 07:04:02 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:15838 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753831AbcGFLD7 (ORCPT ); Wed, 6 Jul 2016 07:03:59 -0400 From: Jisheng Zhang To: , , CC: , , , Jisheng Zhang Subject: [PATCH 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Date: Wed, 6 Jul 2016 18:59:40 +0800 Message-ID: <1467802782-3024-1-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-07-06_05:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1607060098 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org patch1 is a trivial clean up: move the parameters for wait for link into the core pcie-designware.c Since link may be UP but still in link training, if so, we can't think the link is up and operating correctly. So patch2 teaches dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit. Jisheng Zhang (2): PCI: designware: mv parameters for wait for link into pcie-designware.c PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit drivers/pci/host/pcie-designware.c | 11 +++++++++-- drivers/pci/host/pcie-designware.h | 5 ----- 2 files changed, 9 insertions(+), 7 deletions(-) -- 2.8.1