From: Andrew Jeffery <andrew@aj.id.au>
To: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Alexandre Courbot <gnurou@gmail.com>,
Joel Stanley <joel@jms.id.au>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Russell King <linux@armlinux.org.uk>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Jeremy Kerr <jk@ozlabs.org>,
devicetree@vger.kernel.org,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
linux-gpio@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
Alistair Popple <alistair@popple.id.au>
Subject: Re: [PATCH 06/12] gpio: Add Aspeed driver
Date: Fri, 22 Jul 2016 10:19:32 +0930 [thread overview]
Message-ID: <1469148572.5468.2.camel@aj.id.au> (raw)
In-Reply-To: <CAP=VYLrJfRmKOoDWTpBrD5+iPdX6J9r609FzZ0CkzDd7vGBWyw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3705 bytes --]
On Thu, 2016-07-21 at 16:12 -0400, Paul Gortmaker wrote:
> On Wed, Jul 20, 2016 at 1:58 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > From: Joel Stanley <joel@jms.id.au>
> >
> > The Aspeed SoCs contain GPIOs grouped by letter, where each letter group
> > contains 8 pins. The GPIO letter groups are then banked in sets of four
> > in the register layout.
> >
> > The implementation exposes multiple banks through the one driver, and
> > requests and releases pins via the pinctrl subsystem. The hardware
> > supports generation of interrupts with per-pin triggers, and exposes this
> > capability through an irqchip and devicetree.
> >
> > A number of supported features are not yet implemented: Configuration of
> > interrupt direction (ARM or LPC), debouncing, and provides WDT reset
> > tolerance for output ports.
> >
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > Signed-off-by: Alistair Popple <alistair@popple.id.au>
> > Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > arch/arm/mach-aspeed/Kconfig | 4 +
> > drivers/gpio/Kconfig | 8 +-
> > drivers/gpio/Makefile | 1 +
> > drivers/gpio/gpio-aspeed.c | 456 +++++++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 468 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpio/gpio-aspeed.c
> >
> > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
> > index 25a0ae01429e..a52de9d3adfb 100644
> > --- a/arch/arm/mach-aspeed/Kconfig
> > +++ b/arch/arm/mach-aspeed/Kconfig
> > @@ -6,6 +6,10 @@ menuconfig ARCH_ASPEED
> > select ASPEED_WATCHDOG
> > select MOXART_TIMER
> > select PINCTRL
> > + select GPIOLIB
> > + select GPIO_ASPEED
> > + select GPIO_SYSFS
> > +
> > help
> > Say Y here if you want to run your kernel on an ASpeed BMC SoC.
> >
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index 536112fd2466..2c21b5db09cd 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -137,6 +137,13 @@ config GPIO_ATH79
> > Select this option to enable GPIO driver for
> > Atheros AR71XX/AR724X/AR913X SoC devices.
> >
> > +config GPIO_ASPEED
> > + bool "Aspeed GPIO support"
> Since this is a bool Kconfig...
>
> >
> > + depends on (ARCH_ASPEED || COMPILE_TEST) && OF
> > + select GENERIC_IRQ_CHIP
> > + help
> > + Say Y here to support Aspeed AST2400 and AST2500 GPIO controllers.
> > +
> [...]
>
> > diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
> >
> > new file mode 100644
> > index 000000000000..7885adc1332a
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-aspeed.c
> > @@ -0,0 +1,456 @@
> > +/*
> > + * Copyright 2015 IBM Corp
> > + *
> > + * Joel Stanley <joel@jms.id.au>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License
> > + * as published by the Free Software Foundation; either version
> > + * 2 of the License, or (at your option) any later version.
> > + */
> > +
> > +#include
> ...can you please get rid of module.h and all the MODULE_
> stuff and use the built in registration? Alternatively change it to
> a tristate if there is a valid use case for it to be modular.
>
I'll change it to tristate; I don't see a reason to require it be built
in.
Cheers,
Andrew
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
next prev parent reply other threads:[~2016-07-22 0:49 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
2016-07-20 5:58 ` [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
2016-07-20 19:05 ` Rob Herring
2016-07-20 23:13 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs Andrew Jeffery
2016-07-22 6:29 ` Joel Stanley
2016-08-11 8:41 ` Linus Walleij
2016-08-12 0:33 ` Andrew Jeffery
2016-08-12 13:18 ` Linus Walleij
2016-08-13 0:58 ` Benjamin Herrenschmidt
2016-08-15 0:36 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 03/12] pinctrl: Add pinctrl-aspeed-g4 driver Andrew Jeffery
2016-07-20 5:58 ` [PATCH 04/12] pinctrl: Add pinctrl-aspeed-g5 driver Andrew Jeffery
2016-07-20 5:58 ` [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery
2016-07-20 19:06 ` Rob Herring
2016-07-20 5:58 ` [PATCH 06/12] gpio: Add Aspeed driver Andrew Jeffery
2016-07-21 20:12 ` Paul Gortmaker
2016-07-22 0:49 ` Andrew Jeffery [this message]
2016-08-11 9:20 ` Linus Walleij
2016-08-12 0:54 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery
2016-07-20 19:09 ` Rob Herring
2016-07-21 1:04 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 08/12] aspeed-g4: Add syscon and pin controller nodes Andrew Jeffery
2016-07-20 5:58 ` [PATCH 09/12] palmetto: Request relevant mux functions in devicetree Andrew Jeffery
2016-07-20 5:58 ` [PATCH 10/12] aspeed-g4: Add gpio controller to devicetree Andrew Jeffery
2016-07-20 5:58 ` [PATCH 11/12] aspeed-g5: Add syscon and pin controller nodes Andrew Jeffery
2016-07-20 5:58 ` [PATCH 12/12] aspeed-g5: Add gpio controller to devicetree Andrew Jeffery
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1469148572.5468.2.camel@aj.id.au \
--to=andrew@aj.id.au \
--cc=alistair@popple.id.au \
--cc=benh@kernel.crashing.org \
--cc=devicetree@vger.kernel.org \
--cc=gnurou@gmail.com \
--cc=jk@ozlabs.org \
--cc=joel@jms.id.au \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=mark.rutland@arm.com \
--cc=paul.gortmaker@windriver.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox