From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757671AbcG1UcS (ORCPT ); Thu, 28 Jul 2016 16:32:18 -0400 Received: from mail.kymetacorp.com ([192.81.58.21]:23236 "EHLO mail.kymetacorp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752057AbcG1UcR (ORCPT ); Thu, 28 Jul 2016 16:32:17 -0400 X-Greylist: delayed 324 seconds by postgrey-1.27 at vger.kernel.org; Thu, 28 Jul 2016 16:32:16 EDT From: Trent Piepho To: atull CC: Andrea Galbusera , Rob Herring , "pantelis.antoniou@konsulko.com" , "Moritz Fischer" , Josh Cartwright , "gregkh@linuxfoundation.org" , "monstr@monstr.eu" , "michal.simek@xilinx.com" , Pawel Moll , Mark Rutland , "Ian Campbell" , Kumar Gala , Jonathan Corbet , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , "delicious.quinoa@gmail.com" , "dinguyen@opensource.altera.com" , Matthew Gerlach Subject: Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support Thread-Topic: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support Thread-Index: AQHRwr5Pq8+fbGwUtkGsHHTJ+zcoiqAuZV6AgABRyoCAAFXYAA== Date: Thu, 28 Jul 2016 20:26:50 +0000 Message-ID: <1469737696.30803.152.camel@rtred1test09.kymeta.local> References: <1454707803-27947-1-git-send-email-atull@opensource.altera.com> <1454707803-27947-7-git-send-email-atull@opensource.altera.com> <1465525089.15779.203.camel@rtred1test09.kymeta.local> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Evolution 3.8.5 (3.8.5-31.el7) x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.10.42.160] Content-Type: text/plain; charset="utf-8" Content-ID: <386CA76A829DEC49930BFD4EF15396EA@kymetacorp.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u6SKWOVs002639 On Thu, 2016-07-28 at 10:21 -0500, atull wrote: > > > > > > This isn't going work if more than one bridge is used. Each bridge has > > > its own priv and thus priv->l3_remap_value. Each bridge's priv will > > > have just the bit for it's own remap set. The 2nd bridge to be enabled > > > will turn off the 1st bridge when it re-write the l3 register. > > > > I can confirm this is exactly what happens with tag > > "rel_socfpga-4.1.22-ltsi_16.06.02_pr" of socfpga-4.1.22-ltsi branch > > from altera-opensource/linux-socfpga which includes more or less the > > code in this patch. If you have 2 bridges (lw-hps2fpga and hps2fpga) > > you end up with only one of them being visible. Easily spot by logging > > l3_remap_value being passed to regmap_write()... > > > > Anatolij kindly provided a patch for this issue. I'll push it > to my github repo when I can. I still think a better solution would be to allow the syscon driver manage shared access. The purpose of syscon is to manage access to a shared resource from multiple devices. And regmap already has the ability to cache a write-only register and allow thread safe access to modify bits in said register. The problem is just the pain of trying to do anything to syscon DT bindings. Something like "write-only" in the syscon binding that sets a couple values in the regmap_config is all that's necessary. Might as well not use syscon at all and have the bridge driver map the l3regs itself, since it doesn't really use syscon for anything.