From: Lin Huang <hl@rock-chips.com>
To: heiko@sntech.de, cw00.choi@samsung.com
Cc: tixy@linaro.org, dbasehore@chromium.org, airlied@linux.ie,
mturquette@baylibre.com, typ@rock-chips.com,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, dianders@chromium.org,
linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com,
myungjoo.ham@samsung.com, linux-arm-kernel@lists.infradead.org,
mark.yao@rock-chips.com, Lin Huang <hl@rock-chips.com>
Subject: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll
Date: Fri, 29 Jul 2016 15:56:55 +0800 [thread overview]
Message-ID: <1469779021-10426-2-git-send-email-hl@rock-chips.com> (raw)
In-Reply-To: <1469779021-10426-1-git-send-email-hl@rock-chips.com>
From: Heiko Stübner <heiko@sntech.de>
add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
Changes in v1:
- None
drivers/clk/rockchip/clk-pll.c | 4 ++--
drivers/clk/rockchip/clk.c | 2 +-
drivers/clk/rockchip/clk.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 8ac73bc..d824c36 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -864,7 +864,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
u8 num_parents, int con_offset, int grf_lock_offset,
int lock_shift, int mode_offset, int mode_shift,
struct rockchip_pll_rate_table *rate_table,
- u8 clk_pll_flags)
+ unsigned long flags, u8 clk_pll_flags)
{
const char *pll_parents[3];
struct clk_init_data init;
@@ -919,7 +919,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
init.name = pll_name;
/* keep all plls untouched for now */
- init.flags = CLK_IGNORE_UNUSED;
+ init.flags = flags | CLK_IGNORE_UNUSED;
init.parent_names = &parent_names[0];
init.num_parents = 1;
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index f0a8be1..9a046f1 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -390,7 +390,7 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
list->con_offset, grf_lock_offset,
list->lock_shift, list->mode_offset,
list->mode_shift, list->rate_table,
- list->pll_flags);
+ list->flags, list->pll_flags);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 1abb7d0..bac775d 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -238,7 +238,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
u8 num_parents, int con_offset, int grf_lock_offset,
int lock_shift, int mode_offset, int mode_shift,
struct rockchip_pll_rate_table *rate_table,
- u8 clk_pll_flags);
+ unsigned long flags, u8 clk_pll_flags);
struct rockchip_cpuclk_clksel {
int reg;
--
1.9.1
next prev parent reply other threads:[~2016-07-29 7:57 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20160729075805epcas1p2fa2fab53fc8cdfdf42f53e99a0a72e6a@epcas1p2.samsung.com>
2016-07-29 7:56 ` [PATCH v4 0/7] rk3399 support ddr frequency scaling Lin Huang
2016-07-29 7:56 ` Lin Huang [this message]
2016-08-04 22:37 ` [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll Heiko Stuebner
2016-08-05 8:50 ` hl
2016-08-05 8:55 ` Heiko Stübner
2016-07-29 7:56 ` [PATCH v4 2/7] clk: rockchip: add new clock-type for the ddrclk Lin Huang
2016-08-04 20:23 ` Heiko Stübner
2016-08-04 22:42 ` Heiko Stuebner
2016-07-29 7:56 ` [PATCH v4 3/7] clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc Lin Huang
2016-08-04 22:40 ` Heiko Stuebner
2016-07-29 7:56 ` [PATCH v4 4/7] clk: rockchip: rk3399: add ddrc clock support Lin Huang
2016-07-29 7:56 ` [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller Lin Huang
2016-08-01 7:41 ` Chanwoo Choi
2016-08-01 8:08 ` Chanwoo Choi
2016-08-01 8:27 ` hl
2016-08-01 10:31 ` Chanwoo Choi
2016-07-29 7:57 ` [PATCH v4 6/7] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc Lin Huang
2016-08-01 10:28 ` Chanwoo Choi
2016-08-02 1:03 ` hl
2016-08-02 4:21 ` Chanwoo Choi
2016-08-03 7:38 ` hl
2016-08-04 0:33 ` Chanwoo Choi
2016-07-29 7:57 ` [PATCH v4 7/7] drm/rockchip: Add dmc notifier in vop driver Lin Huang
2016-08-01 7:39 ` [PATCH v4 0/7] rk3399 support ddr frequency scaling Chanwoo Choi
2016-08-01 7:46 ` hl
2016-08-01 7:50 ` Chanwoo Choi
2016-08-05 13:48 ` Tomeu Vizoso
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