From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755997AbcHXNhb (ORCPT ); Wed, 24 Aug 2016 09:37:31 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:34875 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754342AbcHXNh1 (ORCPT ); Wed, 24 Aug 2016 09:37:27 -0400 From: Mirza Krak X-Google-Original-From: Mirza Krak < mirza.krak@gmail.com > To: swarren@wwwdotorg.org, thierry.reding@gmail.com, jonathanh@nvidia.com Cc: gnurou@gmail.com, linux@armlinux.org.uk, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Mirza Krak Subject: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Date: Wed, 24 Aug 2016 15:37:13 +0200 Message-Id: <1472045838-22628-2-git-send-email-mirza.krak@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1472045838-22628-1-git-send-email-mirza.krak@gmail.com> References: <1472045838-22628-1-git-send-email-mirza.krak@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mirza Krak Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz which is max rate. Signed-off-by: Mirza Krak --- Changes in v2: - no changes drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 837e5cb..13d3b5a 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 }, { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, -- 2.1.4