From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932613AbcH1VCT (ORCPT ); Sun, 28 Aug 2016 17:02:19 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:34779 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932279AbcH1VCP (ORCPT ); Sun, 28 Aug 2016 17:02:15 -0400 X-IBM-Helo: d28dlp03.in.ibm.com X-IBM-MailFrom: maddy@linux.vnet.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org From: Madhavan Srinivasan To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: Madhavan Srinivasan , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Jiri Olsa , Arnaldo Carvalho de Melo , Stephane Eranian , Russell King , Catalin Marinas , Will Deacon , Benjamin Herrenschmidt , Michael Ellerman , Sukadev Bhattiprolu Subject: [PATCH 08/13] powerpc/perf: Add support for perf_arch_regs for newer Power processor Date: Mon, 29 Aug 2016 02:30:53 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472418058-28659-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1472418058-28659-1-git-send-email-maddy@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16082821-0056-0000-0000-000002DB1109 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16082821-0057-0000-0000-00000FB66D70 Message-Id: <1472418058-28659-9-git-send-email-maddy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-08-28_10:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1608280206 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add code to define support functions and registers mask for Power8 and later processor. Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Jiri Olsa Cc: Arnaldo Carvalho de Melo Cc: Stephane Eranian Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Benjamin Herrenschmidt Cc: Michael Ellerman Cc: Sukadev Bhattiprolu Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/isa207-common.c | 18 ++++++++++++++++++ arch/powerpc/perf/isa207-common.h | 10 ++++++++++ arch/powerpc/perf/power8-pmu.c | 2 ++ arch/powerpc/perf/power9-pmu.c | 2 ++ 4 files changed, 32 insertions(+) diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index 6143c99f3ec5..43931c695ecb 100644 --- a/arch/powerpc/perf/isa207-common.c +++ b/arch/powerpc/perf/isa207-common.c @@ -261,3 +261,21 @@ void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]) if (pmc <= 3) mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); } + +void isa207_get_arch_regs(struct perf_arch_regs *regs) +{ + regs->regs[PERF_ARCH_REG_POWERPC_PVR] = mfspr(SPRN_PVR); + regs->regs[PERF_ARCH_REG_POWERPC_PMC1] = mfspr(SPRN_PMC1); + regs->regs[PERF_ARCH_REG_POWERPC_PMC2] = mfspr(SPRN_PMC2); + regs->regs[PERF_ARCH_REG_POWERPC_PMC3] = mfspr(SPRN_PMC3); + regs->regs[PERF_ARCH_REG_POWERPC_PMC4] = mfspr(SPRN_PMC4); + regs->regs[PERF_ARCH_REG_POWERPC_PMC5] = mfspr(SPRN_PMC5); + regs->regs[PERF_ARCH_REG_POWERPC_PMC6] = mfspr(SPRN_PMC6); + regs->regs[PERF_ARCH_REG_POWERPC_MMCR0] = mfspr(SPRN_MMCR0); + regs->regs[PERF_ARCH_REG_POWERPC_MMCR1] = mfspr(SPRN_MMCR1); + regs->regs[PERF_ARCH_REG_POWERPC_SIER] = mfspr(SPRN_SIER); + regs->regs[PERF_ARCH_REG_POWERPC_SIAR] = mfspr(SPRN_SIAR); + regs->regs[PERF_ARCH_REG_POWERPC_SDAR] = mfspr(SPRN_SDAR); + regs->regs[PERF_ARCH_REG_POWERPC_MMCRA] = mfspr(SPRN_MMCRA); + regs->regs[PERF_ARCH_REG_POWERPC_MMCR2] = mfspr(SPRN_MMCR2); +} diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index 4d0a4e5017c2..94bf8dd548ac 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -16,6 +16,7 @@ #include #include #include +#include /* * Raw event encoding for PowerISA v2.07: @@ -227,10 +228,19 @@ #define MAX_ALT 2 #define MAX_PMU_COUNTERS 6 +#define ISA207_ARCH_REGS_MASK (PERF_ARCH_REG_PVR |\ + PERF_ARCH_REG_PMC1 | PERF_ARCH_REG_PMC2 |\ + PERF_ARCH_REG_PMC3 | PERF_ARCH_REG_PMC4 |\ + PERF_ARCH_REG_PMC5 | PERF_ARCH_REG_PMC6 |\ + PERF_ARCH_REG_MMCR0 | PERF_ARCH_REG_MMCR1 |\ + PERF_ARCH_REG_SIER | PERF_ARCH_REG_SIAR |\ + PERF_ARCH_REG_SDAR | PERF_ARCH_REG_MMCRA | PERF_ARCH_REG_MMCR2) + int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp); int isa207_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]); void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]); +void isa207_get_arch_regs(struct perf_arch_regs *regs); #endif diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c index 5fde2b192fec..8c8bc5083eb2 100644 --- a/arch/powerpc/perf/power8-pmu.c +++ b/arch/powerpc/perf/power8-pmu.c @@ -394,6 +394,8 @@ static struct power_pmu power8_pmu = { .cache_events = &power8_cache_events, .attr_groups = power8_pmu_attr_groups, .bhrb_nr = 32, + .ar_mask = ISA207_ARCH_REGS_MASK, + .get_arch_regs = isa207_get_arch_regs, }; static int __init init_power8_pmu(void) diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c index 788346303852..1e66ec36b90f 100644 --- a/arch/powerpc/perf/power9-pmu.c +++ b/arch/powerpc/perf/power9-pmu.c @@ -307,6 +307,8 @@ static struct power_pmu power9_pmu = { .cache_events = &power9_cache_events, .attr_groups = power9_pmu_attr_groups, .bhrb_nr = 32, + .ar_mask = ISA207_ARCH_REGS_MASK, + .get_arch_regs = isa207_get_arch_regs, }; static int __init init_power9_pmu(void) -- 2.7.4