From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758286AbcHaGhy (ORCPT ); Wed, 31 Aug 2016 02:37:54 -0400 Received: from mail-he1eur01on0123.outbound.protection.outlook.com ([104.47.0.123]:2247 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750849AbcHaGhv (ORCPT ); Wed, 31 Aug 2016 02:37:51 -0400 X-Greylist: delayed 39789 seconds by postgrey-1.27 at vger.kernel.org; Wed, 31 Aug 2016 02:37:50 EDT From: Marcel Ziswiler To: "jonathanh@nvidia.com" , "mirza.krak@gmail.com" , "swarren@wwwdotorg.org" , "thierry.reding@gmail.com" CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "mturquette@baylibre.com" , "pgaikwad@nvidia.com" , "linux@armlinux.org.uk" , "devicetree@vger.kernel.org" , "gnurou@gmail.com" , "mark.rutland@arm.com" , "linux-arm-kernel@lists.infradead.org" , "pdeschrijver@nvidia.com" , "sboyd@codeaurora.org" , "linux-tegra@vger.kernel.org" , "linux-clk@vger.kernel.org" Subject: Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller Thread-Topic: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller Thread-Index: AQHSAs9+anyn3V2k7EOzyuAy5Da4zA== Date: Tue, 30 Aug 2016 15:02:14 +0000 Message-ID: <1472569333.5703.24.camel@toradex.com> References: <1472045838-22628-1-git-send-email-mirza.krak@gmail.com> <1472045838-22628-4-git-send-email-mirza.krak@gmail.com> In-Reply-To: <1472045838-22628-4-git-send-email-mirza.krak@gmail.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=marcel.ziswiler@toradex.com; x-originating-ip: [46.140.72.82] x-ms-office365-filtering-correlation-id: f8f0e0fb-1d20-42bc-e083-08d3d0e6a0e4 x-microsoft-exchange-diagnostics: 1;HE1PR05MB1884;6:ulgbd4Ae1RRKM0bLA7mTcxD6vTMasYp4iPdP1EXJHRp9OK8Z0PzCXW8MwZuVXkjZry413sJZOCqQwLraqcusNIyuYFfXhmg6VfMnXdFe6U4ozahQi5smwLH1DMRIrfWtSBKHrQecZLP/wGMuDlhfsMLIoVibNgErFh5GcijBIgBjarXVh+oGvYcU+GXB5lENOopEg+QizgOTCYCq7lF1Hlht3e/yk9pB4hYjmvuoT26SSahhlwkWZUI0eqwpRGdbFTl/bZ8MdjYuc1CVlB7GHvMqG9petNQKrpmfbjZ5wQw=;5:0VK9GGn7y+/ZPhvcjNHaEGdC0CO3X/wStpcEe1aTvx49T1NYJ3YawKoaEEoFecmncAqx37YUu+rYqguKMImmTZX5Ej6II44atNqI/EJ0ekDZYHCDy6ecFgRYBY2qeIxYc31oMu5zfdY0G4RlQEzQdg==;24:jfdRt+LgVVwYdXIknnxTMWfrfr9WeaEPDgbdsAKlWY7do+1Gsn6S5UYkVAR9p/o5ho1OY118EcIyj2Dve5u3f3b+0uleEsTmj90LKItrZdY=;7:5qeclbxxUVoFpDa24KCeyVy6F2yg7OpwDmzVAdGn7iBg5fo4nxvpRQ90v3pukii2yyhkQMow0BWLdQrS04WsAjBsjwe/ucTwE6SB9tdzGucix4oebVm/9JEQix8/sZOfQkoWQGvafMIHMefLb/a0fcDg9tVVwwRWhIIWro1KWl1hMI9txU0ZB3kidPCtu0ByR4tnZzzoQBiJ2kVVGbAyk8VgXXPMLin9Y5sU5/aZQBePDgwP3CeC87AWG+9i2mle x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:HE1PR05MB1884; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046);SRVR:HE1PR05MB1884;BCL:0;PCL:0;RULEID:;SRVR:HE1PR05MB1884; x-forefront-prvs: 0050CEFE70 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(6009001)(7916002)(189002)(199003)(24454002)(377424004)(19580405001)(54356999)(76176999)(8936002)(5002640100001)(87936001)(86362001)(81156014)(81166006)(8676002)(586003)(3846002)(6116002)(106116001)(7846002)(33646002)(4326007)(101416001)(102836003)(77096005)(2906002)(105586002)(7736002)(305945005)(19580395003)(103116003)(66066001)(97736004)(2900100001)(2201001)(3280700002)(92566002)(5890100001)(2950100001)(68736007)(7416002)(2501003)(50986999)(36756003)(10400500002)(5001770100001)(3660700001)(5660300001)(106356001)(189998001)(122556002);DIR:OUT;SFP:1102;SCL:1;SRVR:HE1PR05MB1884;H:HE1PR05MB1882.eurprd05.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 X-OriginatorOrg: toradex.com X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Aug 2016 15:02:14.8080 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d9995866-0d9b-4251-8315-093f062abab4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR05MB1884 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u7V6bxnI002057 On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: > From: Mirza Krak > > Document the devicetree bindings for the Generic Memory Interface > (GMI) > bus driver found on Tegra SOCs. > > Signed-off-by: Mirza Krak > --- > Changes in v2: > - Updated examples and some information based on comments from Jon > Hunter. > >  .../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 > +++++++++++++++++++++ >  1 file changed, 132 insertions(+) >  create mode 100644 > Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt > > diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20- > gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20- > gmi.txt > new file mode 100644 > index 0000000..8c1e15f > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt > @@ -0,0 +1,132 @@ > +Device tree bindings for NVIDIA Tegra Generic Memory Interface bus > + > +The Generic Memory Interface bus enables memory transfers between > internal and > +external memory. Can be used to attach various high speed devices > such as > +synchronous/asynchronous NOR, FPGA, UARTS and more. > + > +The actual devices are instantiated from the child nodes of a GMI > node. > + > +Required properties: > + - compatible : Should contain one of the following: > +        For Tegra20 must contain "nvidia,tegra20-gmi". > +        For Tegra30 must contain "nvidia,tegra30-gmi". > + - reg: Should contain GMI controller registers location and length. > + - clocks: Must contain an entry for each entry in clock-names. > + - clock-names: Must include the following entries: "gmi" > + - resets : Must contain an entry for each entry in reset-names. > + - reset-names : Must include the following entries: "gmi" > + - #address-cells: The number of cells used to represent physical > base > +   addresses in the GMI address space. Should be 1. > + - #size-cells: The number of cells used to represent the size of an > address > +   range in the GMI address space. Should be 1. > + - ranges: Must be set up to reflect the memory layout with three > integer values > +   for each chip-select line in use (only one entry is supported, > see below > +   comments): > +    > + > +Note that the GMI controller does not have any internal chip-select > address > +decoding, because of that chip-selects either need to be managed via > software > +or by employing external chip-select decoding logic. > + > +If external chip-select logic is used to support multiple devices it > is assumed > +that the devices use the same timing and so are probably the same > type. It also > +assumes that they can fit in the 256MB address range. In this case > only one > +child device is supported which represents the active chip-select > line, see > +examples for more insight. > + > +Required child cs node properties: > + - reg: First entry should contain the active chip-select number > + > +Optional child cs node properties: > + > + - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is > 16bit. > + - nvidia,snor-mux-mode: Enable address/data MUX mode. > + - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle > before data. > +   If omitted it will be asserted with data. > + - nvidia,snor-rdy-inv: RDY signal is active high > + - nvidia,snor-adv-inv: ADV signal is active high > + - nvidia,snor-oe-inv: WE/OE signal is active high > + - nvidia,snor-cs-inv: CS signal is active high > + > +  Note that there is some special handling for the timing values. > +  From Tegra TRM: > +  Programming 0 means 1 clock cycle: actual cycle = programmed cycle > + 1 > + > + - nvidia,snor-muxed-width: Number of cycles MUX address/data > asserted on the > +   bus. Valid values are 0-15, default is 1 > + - nvidia,snor-hold-width: Number of cycles CE stays asserted after > the > +   de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N > +   (in case of MASTER Request). Valid values are 0-15, default is 1 > + - nvidia,snor-adv-width: Number of cycles during which ADV stays > asserted. > +   Valid values are 0-15, default is 1. > + - nvidia,snor-ce-width: Number of cycles before CE is asserted. > +   Valid values are 0-15, default is 4 > + - nvidia,snor-we-width: Number of cycles during which WE stays > asserted. > +   Valid values are 0-15, default is 1 > + - nvidia,snor-oe-width: Number of cycles during which OE stays > asserted. > +   Valid values are 0-255, default is 1 > + - nvidia,snor-wait-width: Number of cycles before READY is > asserted. > +   Valid values are 0-255, default is 3 > + > +Example with two SJA1000 CAN controllers connected to the GMI bus. > We wrap the > +controllers with a simple-bus node since they are all connected to > the same > +chip-select (CS4), in this example external address decoding is > provided: > + > +gmi@70090000 { It's actually 70009000. > + compatible = "nvidia,tegra20-gmi"; > + reg = <0x70009000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&tegra_car TEGRA20_CLK_NOR>; > + clock-names = "gmi"; > + resets = <&tegra_car 42>; > + reset-names = "gmi"; > + ranges = <4 0x48000000 0x7ffffff>; > + > + status = "disabled"; I guess in an example one could even set this to okay. > + > + bus@4 { > + compatible = "simple-bus"; > + reg = <4>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 4 0x40100>; > + > + nvidia,snor-mux-mode; > + nvidia,snor-adv-inv; > + > + can@0 { > + reg = <0 0x100>; > + ... > + }; > + > + can@40000 { > + reg = <0x40000 0x100>; > + ... > + }; > + }; > +}; > + > +Example with one SJA1000 CAN controller connected to the GMI bus > +on CS4: > + > +gmi@70090000 { Same here. > + compatible = "nvidia,tegra20-gmi"; > + reg = <0x70009000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&tegra_car TEGRA20_CLK_NOR>; > + clock-names = "gmi"; > + resets = <&tegra_car 42>; > + reset-names = "gmi"; > + ranges = <4 0x48000000 0x7ffffff>; > + > + status = "disabled"; Same here. > + > + can@4 { > + reg = <4 0x100>; > + ... > + nvidia,snor-mux-mode; > + nvidia,snor-adv-inv; > + }; > +}; > -- > 2.1.4