Re: [PATCH 3/3] perf/x86/rapl: Enable Baytrail/Braswell RAPL support

["Pan, Harry" <harry.pan@intel.com>]

On Tue, 2016-09-13 at 15:41 +0200, Thomas Gleixner wrote:
> On Sun, 11 Sep 2016, Harry Pan wrote:
> > This patch also enables multiple quirks.
> 
> This patch adds a single quirk for Baytrail. 
> 
> Please stop sending out patches 5 seconds after a review. Take your time
Definitely I take this seriously because I felt awkward as well.

> > +	/*
> > +	 * Some Atom processors (BYT/BSW) have 2^ESU microjoules
> > +	 * increment, refer to Software Developers' Manual, Vol. 3C,
> > +	 * Order No. 325384, Table 35-8 of MSR_RAPL_POWER_UNIT.
> > +	 *
> > +	 * TODO: In order to fit BYT/BSW quirk model, here remind
> > +	 *	 this generates timer rate in 80ms; by default
> > +	 *	 ESU of BYT/BSW is 5, so it leads (1000/200)*2^4.
> 
> This sentence is not a sentence and I can't make any sense of it at
> all.
> 
> What's the TODO here? And why is that TODO not addressed in this patch?
> 
I reviewed my sentence and agreed your comment; yes, it is incorrect to
be a "TODO" tag since no decent suggestion/option.

This things is because of the Baytrail/Braswell quirk breaks original
assumption of perf RAPL polling timer rate calculation regarding of
counter overflow case based on 200W; in short, it leads every 80ms
system triggers an event to read counters, and this is concern I want to
comment (wrong tag?) because I could no assess any side effect.
Perhaps I should revise it as "remark" or "caveat" because I do not have
decent suggestion (fulfill "TODO" tag) so far.

Alternately, it shall not affect functionality since I compared w/
powercap driver through sysfs nodes during experiment, yet I am humble
to take any advice to make this patch better.

Sincerely,
Harry