From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932909AbcITKdg (ORCPT ); Tue, 20 Sep 2016 06:33:36 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:42423 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932418AbcITKdd (ORCPT ); Tue, 20 Sep 2016 06:33:33 -0400 From: John Garry To: , , , , CC: , , , , , , , John Garry Subject: [PATCH 0/3] hisi_sas add hip07 support Date: Tue, 20 Sep 2016 18:48:57 +0800 Message-ID: <1474368540-186535-1-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.57E11078.0128,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 5a24dd64a18ec7c8bd973229aa9a21e3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset introduces support for hip07 SoC. The hip07 SoC has the same v2 hw as in hip06. Support for different reference clock is required as some SAS registers need be programmed differently, depending on the refclock rate. Related patchset: - https://patchwork.ozlabs.org/patch/665172/ Once 4.9-rc1 is released, the D03 dts can be updated for the refclock. Note: there will be only 1 D03 dts, UEFI will update the refclock rate for that board in the fdt at boot time. John Garry (3): devicetree: bindings: scsi: hisi_sas add hip07 support hisi_sas: add device tree support for hip07 hisi_sas: add v2 hw support for different refclk Documentation/devicetree/bindings/scsi/hisilicon-sas.txt | 3 ++- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 7 +++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 8 ++++++-- 4 files changed, 17 insertions(+), 3 deletions(-) -- 1.9.1