[PATCH v1 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate

[PATCH v1 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate

[Andy Shevchenko]

Enable MWI mechanism if PCI bus master supports it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/mfd/intel-lpss-pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
index 50e78db..4756153 100644
--- a/drivers/mfd/intel-lpss-pci.c
+++ b/drivers/mfd/intel-lpss-pci.c
@@ -41,6 +41,7 @@ static int intel_lpss_pci_probe(struct pci_dev *pdev,
 
 	/* Probably it is enough to set this for iDMA capable devices only */
 	pci_set_master(pdev);
+	pci_try_set_mwi(pdev);
 
 	ret = intel_lpss_probe(&pdev->dev, info);
 	if (ret)
-- 
2.9.3

Re: [PATCH v1 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate

[Mika Westerberg]

On Thu, Nov 10, 2016 at 04:51:42PM +0200, Andy Shevchenko wrote:
> Enable MWI mechanism if PCI bus master supports it.

Why?

Re: [PATCH v1 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate

[Andy Shevchenko]

On Thu, 2016-11-10 at 16:59 +0200, Mika Westerberg wrote:
> On Thu, Nov 10, 2016 at 04:51:42PM +0200, Andy Shevchenko wrote:
> > Enable MWI mechanism if PCI bus master supports it.
> 
> Why?

It might be potential benefit in some cases. Documentation says that
standard Memory Write might supply more current data than in the CPU
modified cache line and "trashing a line in the cache may trash some
data that is more current that in the memory line". This allows to avoid
potential retries and other performance degradation issues on the bus.
Though, I dunno how to measure it.

Would be enough to extend commit message by this paragraph?

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH v1 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate

[Mika Westerberg]

On Thu, Nov 10, 2016 at 05:22:40PM +0200, Andy Shevchenko wrote:
> On Thu, 2016-11-10 at 16:59 +0200, Mika Westerberg wrote:
> > On Thu, Nov 10, 2016 at 04:51:42PM +0200, Andy Shevchenko wrote:
> > > Enable MWI mechanism if PCI bus master supports it.
> > 
> > Why?
> 
> It might be potential benefit in some cases. Documentation says that
> standard Memory Write might supply more current data than in the CPU
> modified cache line and "trashing a line in the cache may trash some
> data that is more current that in the memory line". This allows to avoid
> potential retries and other performance degradation issues on the bus.
> Though, I dunno how to measure it.
> 
> Would be enough to extend commit message by this paragraph?

That's better, yes.