From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934103AbcKJPWp (ORCPT ); Thu, 10 Nov 2016 10:22:45 -0500 Received: from mga04.intel.com ([192.55.52.120]:15086 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933926AbcKJPWn (ORCPT ); Thu, 10 Nov 2016 10:22:43 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,619,1473145200"; d="scan'208";a="899995661" Message-ID: <1478791360.5295.119.camel@linux.intel.com> Subject: Re: [PATCH v1 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate From: Andy Shevchenko To: Mika Westerberg Cc: Lee Jones , linux-kernel@vger.kernel.org Date: Thu, 10 Nov 2016 17:22:40 +0200 In-Reply-To: <20161110145930.GL1470@lahna.fi.intel.com> References: <20161110145142.159911-1-andriy.shevchenko@linux.intel.com> <20161110145930.GL1470@lahna.fi.intel.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.1-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2016-11-10 at 16:59 +0200, Mika Westerberg wrote: > On Thu, Nov 10, 2016 at 04:51:42PM +0200, Andy Shevchenko wrote: > > Enable MWI mechanism if PCI bus master supports it. > > Why? It might be potential benefit in some cases. Documentation says that standard Memory Write might supply more current data than in the CPU modified cache line and "trashing a line in the cache may trash some data that is more current that in the memory line". This allows to avoid potential retries and other performance degradation issues on the bus. Though, I dunno how to measure it. Would be enough to extend commit message by this paragraph? -- Andy Shevchenko Intel Finland Oy