Re: [PATCH V3] i2c: designware: fix wrong tx/rx fifo for ACPI

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Mon, 2016-12-12 at 21:21 +0200, Mika Westerberg wrote:
> On Mon, Dec 12, 2016 at 09:02:53PM +0200, Andy Shevchenko wrote:
> > > +	tx_fifo_depth = ((param1 >> 16) & 0xff) + 1;
> > > +	rx_fifo_depth = ((param1 >> 8)  & 0xff) + 1;
> > > +	if (!dev->tx_fifo_depth) {
> > > +		dev->tx_fifo_depth = tx_fifo_depth;
> > > +		dev->rx_fifo_depth = rx_fifo_depth;
> > > +	} else if (tx_fifo_depth) {
> > > +		dev->tx_fifo_depth = min_t(u32, dev-
> > > >tx_fifo_depth,
> > > +				tx_fifo_depth);
> > > +		dev->rx_fifo_depth = min_t(u32, dev-
> > > >rx_fifo_depth,
> > > +				rx_fifo_depth);
> > > +	}
> > 
> > So, let's clarify here:
> > Is it possible to have an IP without parameter block enabled? I mean
> > to
> > read something arbitrary (or zeroes, or all-ones) from param1.
> 
> Yes and it is Intel IP. Haswell IIRC and it returned zeroes.

Wow! Missed that.

In case of zeroes returned the above code might break that (if we are
using FIFO size >1byte). tx_fifo_depth will be 1 AFAIU and second
condition will be the case.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy