From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932561AbcLMJOo convert rfc822-to-8bit (ORCPT ); Tue, 13 Dec 2016 04:14:44 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45916 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752456AbcLMJOk (ORCPT ); Tue, 13 Dec 2016 04:14:40 -0500 Message-ID: <1481611645.27088.56.camel@redhat.com> Subject: Re: [RFC 1/5] drm/virtio: add virtio_gpu_alloc_fence() From: Gerd Hoffmann To: Gustavo Padovan Cc: dri-devel@lists.freedesktop.org, robdclark@gmail.com, Gustavo Padovan , David Airlie , "open list:VIRTIO GPU DRIVER" , open list Date: Tue, 13 Dec 2016 07:47:25 +0100 In-Reply-To: <1481575710-12535-1-git-send-email-gustavo@padovan.org> References: <1481575710-12535-1-git-send-email-gustavo@padovan.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Mime-Version: 1.0 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 13 Dec 2016 09:14:40 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, > +struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev) > +{ > + struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; > + struct virtio_gpu_fence *fence; > + unsigned long irq_flags; > + > + fence = kmalloc(sizeof(struct virtio_gpu_fence), GFP_ATOMIC); > + if (!fence) > + return NULL; > + > + spin_lock_irqsave(&drv->lock, irq_flags); > + fence->drv = drv; > + fence->seq = ++drv->sync_seq; > + dma_fence_init(&fence->f, &virtio_fence_ops, &drv->lock, > + drv->context, fence->seq); > + spin_unlock_irqrestore(&drv->lock, irq_flags); seq assignment ... > + > + return fence; > +} > + > int virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev, > struct virtio_gpu_ctrl_hdr *cmd_hdr, > - struct virtio_gpu_fence **fence) > + struct virtio_gpu_fence *fence) > { > struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; > unsigned long irq_flags; > > - *fence = kmalloc(sizeof(struct virtio_gpu_fence), GFP_ATOMIC); > - if ((*fence) == NULL) > - return -ENOMEM; > - > spin_lock_irqsave(&drv->lock, irq_flags); > - (*fence)->drv = drv; > - (*fence)->seq = ++drv->sync_seq; > - dma_fence_init(&(*fence)->f, &virtio_fence_ops, &drv->lock, > - drv->context, (*fence)->seq); ... must stay here. Otherwise requests can be submitted to the virt queue with fence sequence numbers out of order. cheers, Gerd