From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762821AbdAJMGd (ORCPT ); Tue, 10 Jan 2017 07:06:33 -0500 Received: from mga06.intel.com ([134.134.136.31]:18225 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761513AbdAJMG2 (ORCPT ); Tue, 10 Jan 2017 07:06:28 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,344,1477983600"; d="scan'208";a="1110501854" Message-ID: <1484049982.2133.5.camel@linux.intel.com> Subject: Re: [PATCH] serial: 8250_lpss: Unconditionally set PCI master for Quark From: Andy Shevchenko To: Jan Kiszka , Andy Shevchenko Cc: Greg Kroah-Hartman , "linux-serial@vger.kernel.org" , Linux Kernel Mailing List Date: Tue, 10 Jan 2017 14:06:22 +0200 In-Reply-To: <99156264-8525-f5b6-9a67-735bcdd6f399@siemens.com> References: <1d0224cc-10ee-df69-b383-c687e08ed44d@siemens.com> <99156264-8525-f5b6-9a67-735bcdd6f399@siemens.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2017-01-09 at 18:00 +0100, Jan Kiszka wrote: > On 2017-01-05 22:54, Andy Shevchenko wrote: > > On Wed, Jan 4, 2017 at 10:48 PM, Jan Kiszka > > wrote: > > > MSI needs it as well. > > > > > > Should have no practical impact, though, as DMA is always > > > available on > > > the Quark. But given the few users of pci_alloc_irq_vectors so > > > far, this > > > incorrect pattern may spread otherwise. > > > > > > > One question below. > > > > Reviewed-by: Andy Shevchenko > > > > > Fixes: 3f3a46951e02 ("serial: 8250_lpss: set PCI master only for > > > private DMA") > > > Signed-off-by: Jan Kiszka > > > --- > > >  drivers/tty/serial/8250/8250_lpss.c | 3 ++- > > >  1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/tty/serial/8250/8250_lpss.c > > > b/drivers/tty/serial/8250/8250_lpss.c > > > index f09f68a..9315197 100644 > > > --- a/drivers/tty/serial/8250/8250_lpss.c > > > +++ b/drivers/tty/serial/8250/8250_lpss.c > > > @@ -183,7 +183,6 @@ static void qrk_serial_setup_dma(struct > > > lpss8250 *lpss, struct uart_port *port) > > >         if (ret) > > >                 return; > > > > > > -       pci_set_master(pdev); > > >         pci_try_set_mwi(pdev); > > > > Does it make sense to move MWI there as well? > > TBH, I didn't come across the need to enable this bit so far, > specifically not for doing MSI transactions. Is MWI used at all for > MSI > (spec says that MSI is "using a PCI DWORD memory write transaction")? No, it can't. PCIe has no MWI feature at all, but you may have MSI there. > That question is better answered by someone more familiar with such > PCI > details. In most (modern) cases trying MWI is no-op. So, I think you may send v2 of this with my tag without any changes in the code. Thanks! -- Andy Shevchenko Intel Finland Oy