[PATCH 7/8] x86/intel_rdt/mba: Add schemata file support for MBA

[Vikas Shivappa <vikas.shivappa@linux.intel.com>]

Add support to update the MBA throttle_by values for the domains.
The MBA throttle_by values are specified for each domain which is L3
cache. The schemata string is parsed and validated for the correct
throttle_by values.

The throttle_by granularity is 100-max_throttle_by if scale is linear
and 2^n if non-linear scale.  OS then updates the corresponding domain
PQOS_MSRs which are indexed from 0xD50 for MBA.  The schemata APIs for
parsing and validating the schemata input are changed to accommodate
handling of both cbm and throttle values.

Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
---
 arch/x86/include/asm/intel_rdt.h         |  7 ++++
 arch/x86/kernel/cpu/intel_rdt.c          | 35 +++++++++++------
 arch/x86/kernel/cpu/intel_rdt_schemata.c | 66 +++++++++++++++++++++++---------
 3 files changed, 79 insertions(+), 29 deletions(-)

diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index 88725b6..dbf4c6e 100644
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -76,6 +76,8 @@ struct rftype {
  * @no_ctrl:			Specifies max cache cbm or min mem b/w delay.
  * @min_cbm_bits:		Minimum number of consecutive bits to be set
  *				in a cache bit mask
+ * @display_str:		Format string to show schemata
+ * @validate:			API to validate the ctrl values.
  * @info_files:		resctrl info files for the resource
  * @infofiles_len:		Number of info files
  * @max_delay:		Max throttle delay
@@ -99,6 +101,9 @@ struct rdt_resource {
 	int			cbm_len;
 	int			min_cbm_bits;
 	u32			no_ctrl;
+	char			*display_str;
+	int (*validate)		(char *buf, unsigned long *data,
+				  struct rdt_resource *r);
 	struct rftype		*info_files;
 	int			infofiles_len;
 	u32			max_delay;
@@ -142,6 +147,8 @@ struct msr_param {
 
 void rdt_get_cache_infofile(struct rdt_resource *r);
 void rdt_get_mbe_infofile(struct rdt_resource *r);
+int thrtl_validate(char *buf, unsigned long *data, struct rdt_resource *r);
+int cbm_validate(char *buf, unsigned long *data, struct rdt_resource *r);
 
 extern struct mutex rdtgroup_mutex;
 
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index bdfbd1d..9b0a00e 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -138,7 +138,7 @@ static inline bool cache_alloc_hsw_probe(void)
 	return false;
 }
 
-static void rdt_get_mem_config(struct rdt_resource *r)
+static int rdt_get_mem_config(struct rdt_resource *r)
 {
 	union cpuid_0x10_3_eax eax;
 	union cpuid_0x10_x_edx edx;
@@ -155,11 +155,18 @@ static void rdt_get_mem_config(struct rdt_resource *r)
 		r->delay_gran = MAX_MBA_THRTL - r->max_delay;
 
 	rdt_get_mbe_infofile(r);
+	r->validate = thrtl_validate;
+	r->display_str = kstrdup("%d=%d", GFP_KERNEL);
+	if (!r->display_str)
+		return -ENOMEM;
+
 	r->capable = true;
 	r->enabled = true;
+
+	return 0;
 }
 
-static void rdt_get_cache_config(int idx, struct rdt_resource *r)
+static int rdt_get_cache_config(int idx, struct rdt_resource *r)
 {
 	union cpuid_0x10_1_eax eax;
 	union cpuid_0x10_x_edx edx;
@@ -170,8 +177,16 @@ static void rdt_get_cache_config(int idx, struct rdt_resource *r)
 	r->cbm_len = eax.split.cbm_len + 1;
 	r->no_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
 	rdt_get_cache_infofile(r);
+	r->validate = cbm_validate;
+
+	r->display_str = kstrdup("%d=0x%x", GFP_KERNEL);
+	if (!r->display_str)
+		return -ENOMEM;
+
 	r->capable = true;
 	r->enabled = true;
+
+	return 0;
 }
 
 static void rdt_get_cdp_l3_config(int type)
@@ -190,15 +205,15 @@ static void rdt_get_cdp_l3_config(int type)
 	r->enabled = false;
 }
 
-static inline bool get_rdt_resources(void)
+static inline int get_rdt_resources(void)
 {
-	bool ret = false;
+	int ret = 0;
 
 	if (cache_alloc_hsw_probe())
-		return true;
+		return ret;
 
 	if (!boot_cpu_has(X86_FEATURE_RDT_A))
-		return false;
+		return -ENODEV;
 
 	if (boot_cpu_has(X86_FEATURE_CAT_L3)) {
 		rdt_get_cache_config(1, &rdt_resources_all[RDT_RESOURCE_L3]);
@@ -210,13 +225,11 @@ static inline bool get_rdt_resources(void)
 	}
 	if (boot_cpu_has(X86_FEATURE_CAT_L2)) {
 		/* CPUID 0x10.2 fields are same format at 0x10.1 */
-		rdt_get_cache_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
-		ret = true;
+		ret = rdt_get_cache_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
 	}
 
 	if (boot_cpu_has(X86_FEATURE_MBA)) {
-		rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA]);
-		ret = true;
+		ret = rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA]);
 	}
 
 	return ret;
@@ -431,7 +444,7 @@ static int __init intel_rdt_late_init(void)
 	struct rdt_resource *r;
 	int state, ret;
 
-	if (!get_rdt_resources())
+	if (get_rdt_resources())
 		return -ENODEV;
 
 	state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c b/arch/x86/kernel/cpu/intel_rdt_schemata.c
index 054d771..f2205d1 100644
--- a/arch/x86/kernel/cpu/intel_rdt_schemata.c
+++ b/arch/x86/kernel/cpu/intel_rdt_schemata.c
@@ -29,46 +29,75 @@
 #include <asm/intel_rdt.h>
 
 /*
+ * Check whether MBE 'throttle by' value is correct.
+ *	As per the SDM, when the scale is linear the
+ *	throttle_by granularity is '100 - max_thrtl_by'
+ *	and when its non-linear it is 'power of 2'.
+ */
+int thrtl_validate(char *buf, unsigned long *data, struct rdt_resource *r)
+{
+	u32 delay;
+	int ret;
+
+	ret = kstrtoul(buf, 10, data);
+	if (ret)
+		return ret;
+
+	delay = *data;
+	if (delay > r->max_delay ||
+	     (r->delay_linear && (delay % r->delay_gran)) ||
+	     (!r->delay_linear && !is_power_of_2(delay)))
+		return -EINVAL;
+
+	return 0;
+}
+
+/*
  * Check whether a cache bit mask is valid. The SDM says:
  *	Please note that all (and only) contiguous '1' combinations
  *	are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
  * Additionally Haswell requires at least two bits set.
  */
-static bool cbm_validate(unsigned long var, struct rdt_resource *r)
+int cbm_validate(char *buf, unsigned long *data, struct rdt_resource *r)
 {
-	unsigned long first_bit, zero_bit;
+	unsigned long first_bit, zero_bit, var;
+	int ret;
+
+	ret = kstrtoul(buf, 16, &var);
+	if (ret)
+		return ret;
 
 	if (var == 0 || var > r->no_ctrl)
-		return false;
+		return -EINVAL;
 
 	first_bit = find_first_bit(&var, r->cbm_len);
 	zero_bit = find_next_zero_bit(&var, r->cbm_len, first_bit);
 
 	if (find_next_bit(&var, r->cbm_len, zero_bit) < r->cbm_len)
-		return false;
+		return -EINVAL;
 
 	if ((zero_bit - first_bit) < r->min_cbm_bits)
-		return false;
-	return true;
+		return -EINVAL;
+
+	*data = var;
+
+	return 0;
 }
 
 /*
- * Read one cache bit mask (hex). Check that it is valid for the current
- * resource type.
+ * Read the user RDT control value into tempory buffer:
+ * Cache bit mask (hex) or Memory b/w throttle (decimal).
+ * Check that it is valid for the current resource type.
  */
-static int parse_cbm(char *buf, struct rdt_resource *r)
+static int parse_ctrls(char *buf, struct rdt_resource *r)
 {
 	unsigned long data;
-	int ret;
+	int ret = 0;
 
-	ret = kstrtoul(buf, 16, &data);
-	if (ret)
-		return ret;
-	if (!cbm_validate(data, r))
-		return -EINVAL;
+	ret = r->validate(buf, &data, r);
 	r->tmp_ctrl[r->num_tmp_ctrl++] = data;
 
-	return 0;
+	return ret;
 }
 
 /*
@@ -90,7 +119,7 @@ static int parse_line(char *line, struct rdt_resource *r)
 		id = strsep(&dom, "=");
 		if (kstrtoul(id, 10, &dom_id) || dom_id != d->id)
 			return -EINVAL;
-		if (parse_cbm(dom, r))
+		if (parse_ctrls(dom, r))
 			return -EINVAL;
 	}
 
@@ -219,7 +248,8 @@ static void show_doms(struct seq_file *s, struct rdt_resource *r, int closid)
 	list_for_each_entry(dom, &r->domains, list) {
 		if (sep)
 			seq_puts(s, ";");
-		seq_printf(s, "%d=%x", dom->id, dom->ctrl_val[closid]);
+
+		seq_printf(s, r->display_str, dom->id, dom->ctrl_val[closid]);
 		sep = true;
 	}
 	seq_puts(s, "\n");
-- 
1.9.1