From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752187AbdBBRJ0 (ORCPT ); Thu, 2 Feb 2017 12:09:26 -0500 Received: from mga02.intel.com ([134.134.136.20]:12382 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751495AbdBBRJZ (ORCPT ); Thu, 2 Feb 2017 12:09:25 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,325,1477983600"; d="scan'208";a="1121278923" From: thor.thayer@linux.intel.com To: dinguyen@opensource.altera.com, dinh.nguyen@linux.intel.com, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, thor.thayer@linux.intel.com Subject: [PATCH] ARM: dts: Add EMAC AXI settings for Arria10 Date: Thu, 2 Feb 2017 11:09:05 -0600 Message-Id: <1486055345-2894-1-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thor Thayer Add the device tree entries needed to support the EMAC AXI bus settings on the Arria10 SoCFPGA chip. Signed-off-by: Thor Thayer --- arch/arm/boot/dts/socfpga_arria10.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index f520cbf..f05dd15 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -400,6 +400,12 @@ }; }; + socfpga_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <0 0 0 0 16 0 0>; + }; + gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x44 0>; @@ -416,6 +422,7 @@ clock-names = "stmmaceth"; resets = <&rst EMAC0_RESET>; reset-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; -- 2.7.4