From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752117AbdBEHhD (ORCPT ); Sun, 5 Feb 2017 02:37:03 -0500 Received: from regular1.263xmail.com ([211.150.99.134]:59815 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751911AbdBEHhB (ORCPT ); Sun, 5 Feb 2017 02:37:01 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: mark.yao@rock-chips.com X-FST-TO: airlied@linux.ie X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: <3583b2ab4d4aa23d50a5ad339fcad463> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Mark Yao To: David Airlie , Heiko Stuebner , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Yao Subject: [PATCH 2/2] drm/rockchip: dw_hdmi: check display mode with crtc mode valid Date: Sun, 5 Feb 2017 15:36:37 +0800 Message-Id: <1486280197-1585-2-git-send-email-mark.yao@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1486280197-1585-1-git-send-email-mark.yao@rock-chips.com> References: <1486280197-1585-1-git-send-email-mark.yao@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Mark Yao --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 47 +++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index a6d4a02..64408bc 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -158,18 +158,59 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) struct drm_display_mode *mode) { const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; + struct drm_device *dev = connector->dev; + struct drm_encoder *encoder = connector->encoder; + struct rockchip_drm_private *priv = dev->dev_private; int pclk = mode->clock * 1000; - bool valid = false; + enum drm_mode_status status = MODE_BAD; + struct drm_crtc *crtc; int i; for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { if (pclk == mpll_cfg[i].mpixelclock) { - valid = true; + status = MODE_OK; break; } } - return (valid) ? MODE_OK : MODE_BAD; + + if (status != MODE_OK) + return status; + + if (!encoder) { + const struct drm_connector_helper_funcs *funcs; + + funcs = connector->helper_private; + if (funcs->atomic_best_encoder) + encoder = funcs->atomic_best_encoder(connector, + connector->state); + else + encoder = funcs->best_encoder(connector); + } + + if (!encoder || !encoder->possible_crtcs) + return MODE_BAD; + /* + * ensure all drm display mode can work, if someone want support more + * resolutions, please limit the possible_crtc, only connect to + * needed crtc. + */ + drm_for_each_crtc(crtc, connector->dev) { + int pipe = drm_crtc_index(crtc); + const struct rockchip_crtc_funcs *funcs = + priv->crtc_funcs[pipe]; + + if (!(encoder->possible_crtcs & drm_crtc_mask(crtc))) + continue; + if (!funcs || !funcs->mode_valid) + continue; + + status = funcs->mode_valid(crtc, mode); + if (status != MODE_OK) + return status; + } + + return status; } static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = { -- 1.9.1