From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752223AbdBOSgj (ORCPT ); Wed, 15 Feb 2017 13:36:39 -0500 Received: from host.buserror.net ([209.198.135.123]:45687 "EHLO host.buserror.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751313AbdBOSgh (ORCPT ); Wed, 15 Feb 2017 13:36:37 -0500 Message-ID: <1487183790.5636.13.camel@buserror.net> From: Scott Wood To: yuantian.tang@nxp.com, mturquette@baylibre.com Cc: sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Date: Wed, 15 Feb 2017 12:36:30 -0600 In-Reply-To: <1487137656-4006-2-git-send-email-yuantian.tang@nxp.com> References: <1487137656-4006-1-git-send-email-yuantian.tang@nxp.com> <1487137656-4006-2-git-send-email-yuantian.tang@nxp.com> Organization: NXP Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.5.2-0ubuntu3 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 50.171.225.118 X-SA-Exim-Mail-From: oss@buserror.net X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -15 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] * 0.0 URIBL_BLOCKED ADMINISTRATOR NOTICE: The query to URIBL was blocked. * See http://wiki.apache.org/spamassassin/DnsBlocklists#dnsbl-block * for more information. * [URIs: buserror.net] Subject: Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:57:07 +0000) X-SA-Exim-Scanned: Yes (on host.buserror.net) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang@nxp.com wrote: > From: Tang Yuantian > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will be > used for the core PLLs. > > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > --- >  drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++----- Why did you reset the author on these patches?  Have you changed anything?  Why aren't they marked either v2 or resend? -Scott