From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932277AbdBVKs0 (ORCPT ); Wed, 22 Feb 2017 05:48:26 -0500 Received: from mailgw01.mediatek.com ([218.249.47.110]:45123 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1754316AbdBVKsS (ORCPT ); Wed, 22 Feb 2017 05:48:18 -0500 Message-ID: <1487760489.7255.5.camel@mhfsdcap03> Subject: Re: [PATCH v3 7/8] arm64: dts: mt8173: move clock from phy node into port nodes From: Chunfeng Yun To: Sergei Shtylyov CC: Kishon Vijay Abraham I , Matthias Brugger , Felipe Balbi , "Rob Herring" , Mark Rutland , "Ian Campbell" , , , , , Date: Wed, 22 Feb 2017 18:48:09 +0800 In-Reply-To: References: <1487753705-6745-1-git-send-email-chunfeng.yun@mediatek.com> <1487753705-6745-7-git-send-email-chunfeng.yun@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, 2017-02-22 at 12:36 +0300, Sergei Shtylyov wrote: > On 2/22/2017 11:55 AM, Chunfeng Yun wrote: > > > there is a reference clock for each port, HighSpeed port is 48M, > > and SuperSpeed port is 26M which usually comes from 26M oscillator > > directly, but some SoCs is not. it is flexible to move it into port > > ... but on some SoCs does not? I mean the reference clock of SuperSpeed port comes from PLL and need be controlled by driver on some SoCs. When it comes from oscillator directly, it is optional and is ok whether the driver controll it or not > > > node. > > > > Signed-off-by: Chunfeng Yun > [...] > > MBR, Sergei >