[PATCH] irqchip/gic: Don't write to GICD_ICFGR0

[Mikko Perttunen <mperttunen@nvidia.com>]

From: Matt Craighead <mcraighead@nvidia.com>

According to the GICv2 specification, the GICD_ICFGR0,
or GIC_DIST_CONFIG[0] register is read-only. Therefore
avoid writing to it.

Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
[mperttunen@nvidia.com: commit message rewritten]
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/irqchip/irq-gic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 1b1df4f770bd..d9c0000050e0 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -609,7 +609,7 @@ void gic_dist_restore(struct gic_chip_data *gic)
 
 	writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
 
-	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
+	for (i = 1; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 		writel_relaxed(gic->saved_spi_conf[i],
 			dist_base + GIC_DIST_CONFIG + i * 4);
 
@@ -699,7 +699,7 @@ void gic_cpu_restore(struct gic_chip_data *gic)
 	}
 
 	ptr = raw_cpu_ptr(gic->saved_ppi_conf);
-	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
+	for (i = 1; i < DIV_ROUND_UP(32, 16); i++)
 		writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
 
 	for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
-- 
2.1.4