From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751092AbdEASOz (ORCPT ); Mon, 1 May 2017 14:14:55 -0400 Received: from host.buserror.net ([209.198.135.123]:48856 "EHLO host.buserror.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750806AbdEASOp (ORCPT ); Mon, 1 May 2017 14:14:45 -0400 Message-ID: <1493662461.25397.29.camel@buserror.net> From: Scott Wood To: christophe leroy Cc: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Date: Mon, 01 May 2017 13:14:21 -0500 In-Reply-To: References: <20170309094204.ACF5567992@localhost.localdomain> <20170430064826.fags33gcyvpqigah@home.buserror.net> Organization: NXP Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 50.171.225.118 X-SA-Exim-Rcpt-To: christophe.leroy@c-s.fr, benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: oss@buserror.net X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -15 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] * -1.5 GREYLIST_ISWHITE The incoming server has been whitelisted for this * recipient and sender Subject: Re: powerpc/8xx: Adding support of IRQ in MPC8xx GPIO X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:57:07 +0000) X-SA-Exim-Scanned: Yes (on host.buserror.net) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2017-05-01 at 09:46 +0200, christophe leroy wrote: > > Le 30/04/2017 à 08:48, Scott Wood a écrit : > > On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote: > > > > > > @@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np) > > > > > >   spin_lock_init(&cpm1_gc->lock); > > > > > > + if (!of_property_read_u16(np, "interrupts-mask", &mask)) { > > > + int i, j; > > > + > > > + for (i = 0, j = 0; i < 16; i++) > > > + if (mask & (1 << (15 - i))) > > > + cpm1_gc->irq[i] = > > > irq_of_parse_and_map(np, j++); > > > + } > > > > Do we really need to use MSB-first bit numbering here? > > Well, I think it is better to keep the GPIOs in the same order as in the  > CPM1 registers, like everywhere else in that driver, isn't it ? > > The registers have GPIO 0 in the MSB and GPIO15 in the LSB. OK, if there's a specific register this is reflecting that's reasonable. -Scott