From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755828AbdESKbB (ORCPT ); Fri, 19 May 2017 06:31:01 -0400 Received: from gate.crashing.org ([63.228.1.57]:38338 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755667AbdESKa7 (ORCPT ); Fri, 19 May 2017 06:30:59 -0400 Message-ID: <1495189806.3092.111.camel@kernel.crashing.org> Subject: Re: [PATCH 4/4] arch/powerpc/44x/fsp2: wdt tcr update instead of whole rewrite From: Benjamin Herrenschmidt To: Ivan Mikhaylov , Alistair Popple , Matt Porter Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Joel Stanley , Paul Mackerras , Michael Ellerman Date: Fri, 19 May 2017 20:30:06 +1000 In-Reply-To: <20170515130754.59363-5-ivan@de.ibm.com> References: <20170515130754.59363-5-ivan@de.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6 (3.22.6-2.fc25) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2017-05-15 at 16:07 +0300, Ivan Mikhaylov wrote: > +#ifdef CONFIG_FSP2 > +       /* > +        * Prevent a kernel panic caused by unintentionally clearing TCR > +        * watchdog bits.  At this point in the kernel boot, the watchdog has > +        * already been enabled by u-boot.  The original code's attempt to > +        * write to the TCR register results in an inadvertent clearing of the > +        * watchdog configuration bits, causing the 440 to reset. > +        */ > +       tcr = mfspr(SPRN_TCR); > +       tcr &= TCR_WP_MASK; /* clear all bits except for TCR[WP] */ > +       tcr |= TCR_DIE; /* enable decrementer */ > +       mtspr(SPRN_TCR, tcr); > +#else This should be a runtime test, not a compile time option. Cheers, Ben.