From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753797AbdESL3A convert rfc822-to-8bit (ORCPT ); Fri, 19 May 2017 07:29:00 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44858 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750793AbdESL26 (ORCPT ); Fri, 19 May 2017 07:28:58 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 5A11B80478 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=kraxel@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 5A11B80478 Message-ID: <1495193335.627.66.camel@redhat.com> Subject: Re: [PATCH v2 4/5] drm/i915/gvt: Dmabuf support for GVT-g From: Gerd Hoffmann To: Xiaoguang Chen Cc: alex.williamson@redhat.com, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, intel-gvt-dev@lists.freedesktop.org, zhi.a.wang@intel.com, kevin.tian@intel.com Date: Fri, 19 May 2017 13:28:55 +0200 In-Reply-To: <1495101005-16045-5-git-send-email-xiaoguang.chen@intel.com> References: <1495101005-16045-1-git-send-email-xiaoguang.chen@intel.com> <1495101005-16045-5-git-send-email-xiaoguang.chen@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Mime-Version: 1.0 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 19 May 2017 11:28:58 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > +/** > + * Ioctl to query plane info or create dma-buf > + */ > +#define INTEL_VGPU_QUERY_DMABUF 0 > +#define INTEL_VGPU_GENERATE_DMABUF 1 This should use _IO* #defines. > +struct intel_vgpu_dmabuf { > + __u32 plane_id; > + /* out */ > + __u32 fd; > + __u32 drm_format; > + __u32 width; > + __u32 height; > + __u32 stride; > + __u32 start; > + __u32 x_pos; > + __u32 y_pos; > + __u32 size; > + __u32 tiled; I'd suggest to drop tiled, and add drm_format_mod (for fourcc_mod_code()) instead. You can also move intel_vgpu_plane_info to this place and just use it as sub-struct for intel_vgpu_dmabuf. cheers, Gerd