[PATCH 3/3] drm/radeon: Cleanup pageflipping IRQ handling for evergreen, si

Lyude
2017-05-16T21:12:34Z

Same as the previous patch, but for pageflipping now.

Signed-off-by: Lyude <lyude@redhat.com>
---
drivers/gpu/drm/radeon/evergreen.c | 70 ++++++------------------------------
drivers/gpu/drm/radeon/radeon.h | 7 +---
drivers/gpu/drm/radeon/si.c | 72 ++++++--------------------------------
3 files changed, 22 insertions(+), 127 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 76a2f20..3bfc951 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4452,18 +4452,9 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
WREG32(DMA_CNTL, tmp);
WREG32(GRBM_INT_CNTL, 0);
WREG32(SRBM_INT_CNTL, 0);
- for (i = 0; i < rdev->num_crtc; i++)
+ for (i = 0; i < rdev->num_crtc; i++) {
WREG32(INT_MASK + crtc_offsets[i], 0);
-
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
- if (rdev->num_crtc >= 4) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
- }
- if (rdev->num_crtc >= 6) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+ WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
}

/* only one DAC on DCE5 */
@@ -4559,23 +4550,6 @@ int evergreen_irq_set(struct radeon_device *rdev)

WREG32(GRBM_INT_CNTL, grbm_int_cntl);

- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- if (rdev->num_crtc >= 4) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- }
- if (rdev->num_crtc >= 6) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- }
-
for (i = 0; i < EVERGREEN_MAX_DISP_REGISTERS; i++) {
radeon_irq_kms_set_irq_n_enabled(rdev,
DC_HPDx_INT_CONTROL(i),
@@ -4594,6 +4568,9 @@ int evergreen_irq_set(struct radeon_device *rdev)
rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK,
rdev->irq.crtc_vblank_int[i] ||
atomic_read(&rdev->irq.pflip[i]), "vblank", i);
+
+ WREG32(GRPH_INT_CONTROL + crtc_offsets[i],
+ GRPH_PFLIP_INT_MASK);
}
}

@@ -4611,6 +4588,7 @@ int evergreen_irq_set(struct radeon_device *rdev)
static void evergreen_irq_ack(struct radeon_device *rdev)
{
int i;
+ u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;
u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;

@@ -4627,45 +4605,19 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
AFMT_AZ_FORMAT_WTRIG_ACK);

if (i < rdev->num_crtc) {
+ grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
+
if (disp_int[i] & LB_Dx_VBLANK_INTERRUPT)
WREG32(VBLANK_STATUS + crtc_offsets[i],
VBLANK_ACK);
if (disp_int[i] & LB_Dx_VLINE_INTERRUPT)
WREG32(VLINE_STATUS + crtc_offsets[i],
VLINE_ACK);
+ if (grph_int[i] & GRPH_PFLIP_INT_OCCURRED)
+ WREG32(GRPH_INT_STATUS + crtc_offsets[i],
+ GRPH_PFLIP_INT_CLEAR);
}
}
-
- rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
- if (rdev->num_crtc >= 4) {
- rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
- }
- if (rdev->num_crtc >= 6) {
- rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
- }
-
-
- if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
-
- if (rdev->num_crtc >= 4) {
- if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- }
-
- if (rdev->num_crtc >= 6) {
- if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- }
}

static void evergreen_irq_disable(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index e961a8a..edb9686 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -768,12 +768,7 @@ struct r600_irq_stat_regs {

struct evergreen_irq_stat_regs {
u32 disp_int[6];
- u32 d1grph_int;
- u32 d2grph_int;
- u32 d3grph_int;
- u32 d4grph_int;
- u32 d5grph_int;
- u32 d6grph_int;
+ u32 grph_int[6];
u32 afmt_status[6];
};

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index bb745e1..7c28689 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5940,20 +5940,9 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
WREG32(GRBM_INT_CNTL, 0);
WREG32(SRBM_INT_CNTL, 0);
- for (i = 0; i < rdev->num_crtc; i++)
+ for (i = 0; i < rdev->num_crtc; i++) {
WREG32(INT_MASK + crtc_offsets[i], 0);
-
- if (rdev->num_crtc >= 2) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
- }
- if (rdev->num_crtc >= 4) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
- }
- if (rdev->num_crtc >= 6) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+ WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
}

if (!ASIC_IS_NODCE(rdev)) {
@@ -6103,25 +6092,6 @@ int si_irq_set(struct radeon_device *rdev)
thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
}

- if (rdev->num_crtc >= 2) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- }
- if (rdev->num_crtc >= 4) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- }
- if (rdev->num_crtc >= 6) {
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
- GRPH_PFLIP_INT_MASK);
- }
-
if (!ASIC_IS_NODCE(rdev)) {
for (i = 0; i < SI_MAX_DISP_REGISTERS; i++) {
radeon_irq_kms_set_irq_n_enabled(
@@ -6136,6 +6106,8 @@ int si_irq_set(struct radeon_device *rdev)
rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK,
rdev->irq.crtc_vblank_int[i] ||
atomic_read(&rdev->irq.pflip[i]), "vblank", i);
+
+ WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
}

WREG32(CG_THERMAL_INT, thermal_int);
@@ -6150,21 +6122,11 @@ static inline void si_irq_ack(struct radeon_device *rdev)
{
int i;
u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
+ u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;

if (ASIC_IS_NODCE(rdev))
return;

- rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
- if (rdev->num_crtc >= 4) {
- rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
- }
- if (rdev->num_crtc >= 6) {
- rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
- }
-
for (i = 0; i < SI_MAX_DISP_REGISTERS; i++) {
disp_int[i] = RREG32(DISP_INTERRUPT_STATUS(i));

@@ -6174,33 +6136,19 @@ static inline void si_irq_ack(struct radeon_device *rdev)
WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK);

if (i < rdev->num_crtc) {
+ grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
+
if (disp_int[i] & LB_Dx_VBLANK_INTERRUPT)
WREG32(VBLANK_STATUS + crtc_offsets[i],
VBLANK_ACK);
if (disp_int[i] & LB_Dx_VLINE_INTERRUPT)
WREG32(VLINE_STATUS + crtc_offsets[i],
VLINE_ACK);
+ if (grph_int[i] & GRPH_PFLIP_INT_OCCURRED)
+ WREG32(GRPH_INT_STATUS + crtc_offsets[i],
+ GRPH_PFLIP_INT_CLEAR);
}
}
-
- if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
-
- if (rdev->num_crtc >= 4) {
- if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- }
-
- if (rdev->num_crtc >= 6) {
- if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
- WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- }
}

static void si_irq_disable(struct radeon_device *rdev)
--
2.9.4