From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752293AbdGFIf6 (ORCPT ); Thu, 6 Jul 2017 04:35:58 -0400 Received: from esa5.microchip.iphmx.com ([216.71.150.166]:1686 "EHLO esa5.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751659AbdGFIfx (ORCPT ); Thu, 6 Jul 2017 04:35:53 -0400 X-IronPort-AV: E=Sophos;i="5.40,316,1496127600"; d="scan'208";a="2040153" From: Claudiu Beznea To: , , , , , CC: , , , , , Cyrille Pitchen , Claudiu Beznea Subject: [PATCH v3 1/5] ARM: dts: at91: sama5d2: add QSPI nodes Date: Thu, 6 Jul 2017 11:35:25 +0300 Message-ID: <1499330129-29319-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499330129-29319-1-git-send-email-claudiu.beznea@microchip.com> References: <1499330129-29319-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Cyrille Pitchen This patch adds DT nodes for sama5d2 QSPI controllers. Signed-off-by: Cyrille Pitchen [claudiu.beznea@microchip.com: change subject to match the desired prefix] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/sama5d2.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index cc06da3..71e9d83 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -954,6 +954,28 @@ }; }; + qspi0: spi@f0020000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&qspi0_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@f0024000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&qspi1_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sha@f0028000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xf0028000 0x100>; -- 2.7.4