* [PATCH v3 01/22] staging: ccree: fix split strings
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 02/22] staging: ccree: kmalloc by sizeof var not type Gilad Ben-Yossef
` (21 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Fix strings in log messages being split across lines and the resulting
alignment issues when being fixed.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_aead.c | 9 ++--
drivers/staging/ccree/ssi_buffer_mgr.c | 86 ++++++++++++++-------------------
drivers/staging/ccree/ssi_cipher.c | 27 +++++------
drivers/staging/ccree/ssi_driver.c | 4 +-
drivers/staging/ccree/ssi_hash.c | 43 ++++++++---------
drivers/staging/ccree/ssi_ivgen.c | 8 +--
drivers/staging/ccree/ssi_request_mgr.c | 13 ++---
7 files changed, 81 insertions(+), 109 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index f5ca0e3..d8f2249 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -240,9 +240,8 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c
if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
if (memcmp(areq_ctx->mac_buf, areq_ctx->icv_virt_addr,
ctx->authsize) != 0) {
- SSI_LOG_DEBUG("Payload authentication failure, "
- "(auth-size=%d, cipher=%d).\n",
- ctx->authsize, ctx->cipher_mode);
+ SSI_LOG_DEBUG("Payload authentication failure, (auth-size=%d, cipher=%d).\n",
+ ctx->authsize, ctx->cipher_mode);
/* In case of payload authentication failure, MUST NOT
* revealed the decrypted message --> zero its memory.
*/
@@ -455,8 +454,8 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl
if (likely(keylen != 0)) {
key_dma_addr = dma_map_single(dev, (void *)key, keylen, DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, key_dma_addr))) {
- SSI_LOG_ERR("Mapping key va=0x%p len=%u for"
- " DMA failed\n", key, keylen);
+ SSI_LOG_ERR("Mapping key va=0x%p len=%u for DMA failed\n",
+ key, keylen);
return -ENOMEM;
}
if (keylen > blocksize) {
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c
index 6393609..d7ce293 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -82,8 +82,8 @@ static unsigned int ssi_buffer_mgr_get_sgl_nents(
while (nbytes != 0) {
if (sg_is_chain(sg_list)) {
- SSI_LOG_ERR("Unexpected chained entry "
- "in sg (entry =0x%X)\n", nents);
+ SSI_LOG_ERR("Unexpected chained entry in sg (entry =0x%X)\n",
+ nents);
BUG();
}
if (sg_list->length != 0) {
@@ -259,11 +259,9 @@ static int ssi_buffer_mgr_generate_mlli(
/* Set MLLI size for the bypass operation */
mlli_params->mlli_len = (total_nents * LLI_ENTRY_BYTE_SIZE);
- SSI_LOG_DEBUG("MLLI params: "
- "virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n",
- mlli_params->mlli_virt_addr,
- mlli_params->mlli_dma_addr,
- mlli_params->mlli_len);
+ SSI_LOG_DEBUG("MLLI params: virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n",
+ mlli_params->mlli_virt_addr, mlli_params->mlli_dma_addr,
+ mlli_params->mlli_len);
build_mlli_exit:
return rc;
@@ -276,9 +274,8 @@ static inline void ssi_buffer_mgr_add_buffer_entry(
{
unsigned int index = sgl_data->num_of_buffers;
- SSI_LOG_DEBUG("index=%u single_buff=%pad "
- "buffer_len=0x%08X is_last=%d\n",
- index, buffer_dma, buffer_len, is_last_entry);
+ SSI_LOG_DEBUG("index=%u single_buff=%pad buffer_len=0x%08X is_last=%d\n",
+ index, buffer_dma, buffer_len, is_last_entry);
sgl_data->nents[index] = 1;
sgl_data->entry[index].buffer_dma = buffer_dma;
sgl_data->offset[index] = 0;
@@ -359,8 +356,7 @@ static int ssi_buffer_mgr_map_scatterlist(
SSI_LOG_ERR("dma_map_sg() single buffer failed\n");
return -ENOMEM;
}
- SSI_LOG_DEBUG("Mapped sg: dma_address=%pad "
- "page=%p addr=%pK offset=%u "
+ SSI_LOG_DEBUG("Mapped sg: dma_address=%pad page=%p addr=%pK offset=%u "
"length=%u\n",
sg_dma_address(sg),
sg_page(sg),
@@ -419,12 +415,10 @@ ssi_aead_handle_config_buf(struct device *dev,
sg_init_one(&areq_ctx->ccm_adata_sg, config_data, AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size);
if (unlikely(dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1,
DMA_TO_DEVICE) != 1)) {
- SSI_LOG_ERR("dma_map_sg() "
- "config buffer failed\n");
+ SSI_LOG_ERR("dma_map_sg() config buffer failed\n");
return -ENOMEM;
}
- SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad "
- "page=%p addr=%pK "
+ SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad page=%p addr=%pK "
"offset=%u length=%u\n",
sg_dma_address(&areq_ctx->ccm_adata_sg),
sg_page(&areq_ctx->ccm_adata_sg),
@@ -452,12 +446,10 @@ static inline int ssi_ahash_handle_curr_buf(struct device *dev,
sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt);
if (unlikely(dma_map_sg(dev, areq_ctx->buff_sg, 1,
DMA_TO_DEVICE) != 1)) {
- SSI_LOG_ERR("dma_map_sg() "
- "src buffer failed\n");
+ SSI_LOG_ERR("dma_map_sg() src buffer failed\n");
return -ENOMEM;
}
- SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad "
- "page=%p addr=%pK "
+ SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad page=%p addr=%pK "
"offset=%u length=%u\n",
sg_dma_address(areq_ctx->buff_sg),
sg_page(areq_ctx->buff_sg),
@@ -539,8 +531,8 @@ int ssi_buffer_mgr_map_blkcipher_request(
DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev,
req_ctx->gen_ctx.iv_dma_addr))) {
- SSI_LOG_ERR("Mapping iv %u B at va=%pK "
- "for DMA failed\n", ivsize, info);
+ SSI_LOG_ERR("Mapping iv %u B at va=%pK for DMA failed\n",
+ ivsize, info);
return -ENOMEM;
}
SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=%pad\n",
@@ -1340,9 +1332,9 @@ int ssi_buffer_mgr_map_aead_request(
DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, areq_ctx->ccm_iv0_dma_addr))) {
- SSI_LOG_ERR("Mapping mac_buf %u B at va=%pK "
- "for DMA failed\n", AES_BLOCK_SIZE,
- (areq_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET));
+ SSI_LOG_ERR("Mapping mac_buf %u B at va=%pK for DMA failed\n",
+ AES_BLOCK_SIZE, (areq_ctx->ccm_config +
+ CCM_CTR_COUNT_0_OFFSET));
areq_ctx->ccm_iv0_dma_addr = 0;
rc = -ENOMEM;
goto aead_map_failure;
@@ -1385,9 +1377,8 @@ int ssi_buffer_mgr_map_aead_request(
DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_iv_inc1_dma_addr))) {
- SSI_LOG_ERR("Mapping gcm_iv_inc1 %u B at va=%pK "
- "for DMA failed\n", AES_BLOCK_SIZE,
- (areq_ctx->gcm_iv_inc1));
+ SSI_LOG_ERR("Mapping gcm_iv_inc1 %u B at va=%pK for DMA failed\n",
+ AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc1));
areq_ctx->gcm_iv_inc1_dma_addr = 0;
rc = -ENOMEM;
goto aead_map_failure;
@@ -1399,9 +1390,8 @@ int ssi_buffer_mgr_map_aead_request(
DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_iv_inc2_dma_addr))) {
- SSI_LOG_ERR("Mapping gcm_iv_inc2 %u B at va=%pK "
- "for DMA failed\n", AES_BLOCK_SIZE,
- (areq_ctx->gcm_iv_inc2));
+ SSI_LOG_ERR("Mapping gcm_iv_inc2 %u B at va=%pK for DMA failed\n",
+ AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc2));
areq_ctx->gcm_iv_inc2_dma_addr = 0;
rc = -ENOMEM;
goto aead_map_failure;
@@ -1507,8 +1497,7 @@ int ssi_buffer_mgr_map_hash_request_final(
u32 dummy = 0;
u32 mapped_nents = 0;
- SSI_LOG_DEBUG(" final params : curr_buff=%pK "
- "curr_buff_cnt=0x%X nbytes = 0x%X "
+ SSI_LOG_DEBUG(" final params : curr_buff=%pK curr_buff_cnt=0x%X nbytes = 0x%X "
"src=%pK curr_index=%u\n",
curr_buff, *curr_buff_cnt, nbytes,
src, areq_ctx->buff_index);
@@ -1604,8 +1593,7 @@ int ssi_buffer_mgr_map_hash_request_update(
u32 dummy = 0;
u32 mapped_nents = 0;
- SSI_LOG_DEBUG(" update params : curr_buff=%pK "
- "curr_buff_cnt=0x%X nbytes=0x%X "
+ SSI_LOG_DEBUG(" update params : curr_buff=%pK curr_buff_cnt=0x%X nbytes=0x%X "
"src=%pK curr_index=%u\n",
curr_buff, *curr_buff_cnt, nbytes,
src, areq_ctx->buff_index);
@@ -1617,10 +1605,9 @@ int ssi_buffer_mgr_map_hash_request_update(
areq_ctx->in_nents = 0;
if (unlikely(total_in_len < block_size)) {
- SSI_LOG_DEBUG(" less than one block: curr_buff=%pK "
- "*curr_buff_cnt=0x%X copy_to=%pK\n",
- curr_buff, *curr_buff_cnt,
- &curr_buff[*curr_buff_cnt]);
+ SSI_LOG_DEBUG(" less than one block: curr_buff=%pK *curr_buff_cnt=0x%X copy_to=%pK\n",
+ curr_buff, *curr_buff_cnt,
+ &curr_buff[*curr_buff_cnt]);
areq_ctx->in_nents =
ssi_buffer_mgr_get_sgl_nents(src,
nbytes,
@@ -1636,16 +1623,14 @@ int ssi_buffer_mgr_map_hash_request_update(
/* update data len */
update_data_len = total_in_len - *next_buff_cnt;
- SSI_LOG_DEBUG(" temp length : *next_buff_cnt=0x%X "
- "update_data_len=0x%X\n",
- *next_buff_cnt, update_data_len);
+ SSI_LOG_DEBUG(" temp length : *next_buff_cnt=0x%X update_data_len=0x%X\n",
+ *next_buff_cnt, update_data_len);
/* Copy the new residue to next buffer */
if (*next_buff_cnt != 0) {
- SSI_LOG_DEBUG(" handle residue: next buff %pK skip data %u"
- " residue %u\n", next_buff,
- (update_data_len - *curr_buff_cnt),
- *next_buff_cnt);
+ SSI_LOG_DEBUG(" handle residue: next buff %pK skip data %u residue %u\n",
+ next_buff, (update_data_len - *curr_buff_cnt),
+ *next_buff_cnt);
ssi_buffer_mgr_copy_scatterlist_portion(next_buff, src,
(update_data_len - *curr_buff_cnt),
nbytes, SSI_SG_TO_BUF);
@@ -1743,11 +1728,10 @@ void ssi_buffer_mgr_unmap_hash_request(
}
if (*prev_len != 0) {
- SSI_LOG_DEBUG("Unmapped buffer: areq_ctx->buff_sg=%pK"
- " dma=%pad len 0x%X\n",
- sg_virt(areq_ctx->buff_sg),
- sg_dma_address(areq_ctx->buff_sg),
- sg_dma_len(areq_ctx->buff_sg));
+ SSI_LOG_DEBUG("Unmapped buffer: areq_ctx->buff_sg=%pK dma=%pad len 0x%X\n",
+ sg_virt(areq_ctx->buff_sg),
+ sg_dma_address(areq_ctx->buff_sg),
+ sg_dma_len(areq_ctx->buff_sg));
dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
if (!do_revert) {
/* clean the previous data length for update operation */
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index 6219a92..068b10b 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -636,11 +636,10 @@ ssi_blkcipher_create_data_desc(
(*seq_size)++;
} else {
/* bypass */
- SSI_LOG_DEBUG(" bypass params addr %pad "
- "length 0x%X addr 0x%08X\n",
- req_ctx->mlli_params.mlli_dma_addr,
- req_ctx->mlli_params.mlli_len,
- (unsigned int)ctx_p->drvdata->mlli_sram_addr);
+ SSI_LOG_DEBUG(" bypass params addr %pad length 0x%X addr 0x%08X\n",
+ req_ctx->mlli_params.mlli_dma_addr,
+ req_ctx->mlli_params.mlli_len,
+ (unsigned int)ctx_p->drvdata->mlli_sram_addr);
hw_desc_init(&desc[*seq_size]);
set_din_type(&desc[*seq_size], DMA_DLLI,
req_ctx->mlli_params.mlli_dma_addr,
@@ -656,21 +655,19 @@ ssi_blkcipher_create_data_desc(
ctx_p->drvdata->mlli_sram_addr,
req_ctx->in_mlli_nents, NS_BIT);
if (req_ctx->out_nents == 0) {
- SSI_LOG_DEBUG(" din/dout params addr 0x%08X "
- "addr 0x%08X\n",
- (unsigned int)ctx_p->drvdata->mlli_sram_addr,
- (unsigned int)ctx_p->drvdata->mlli_sram_addr);
+ SSI_LOG_DEBUG(" din/dout params addr 0x%08X addr 0x%08X\n",
+ (unsigned int)ctx_p->drvdata->mlli_sram_addr,
+ (unsigned int)ctx_p->drvdata->mlli_sram_addr);
set_dout_mlli(&desc[*seq_size],
ctx_p->drvdata->mlli_sram_addr,
req_ctx->in_mlli_nents, NS_BIT,
(!areq ? 0 : 1));
} else {
- SSI_LOG_DEBUG(" din/dout params "
- "addr 0x%08X addr 0x%08X\n",
- (unsigned int)ctx_p->drvdata->mlli_sram_addr,
- (unsigned int)ctx_p->drvdata->mlli_sram_addr +
- (u32)LLI_ENTRY_BYTE_SIZE *
- req_ctx->in_nents);
+ SSI_LOG_DEBUG(" din/dout params addr 0x%08X addr 0x%08X\n",
+ (unsigned int)ctx_p->drvdata->mlli_sram_addr,
+ (unsigned int)ctx_p->drvdata->mlli_sram_addr +
+ (u32)LLI_ENTRY_BYTE_SIZE *
+ req_ctx->in_nents);
set_dout_mlli(&desc[*seq_size],
(ctx_p->drvdata->mlli_sram_addr +
(LLI_ENTRY_BYTE_SIZE *
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index a4ab9ef..d104dbd 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -257,8 +257,8 @@ static int init_cc_resources(struct platform_device *plat_dev)
/* Map registers space */
req_mem_cc_regs = request_mem_region(new_drvdata->res_mem->start, resource_size(new_drvdata->res_mem), "arm_cc7x_regs");
if (unlikely(!req_mem_cc_regs)) {
- SSI_LOG_ERR("Couldn't allocate registers memory region at "
- "0x%08X\n", (unsigned int)new_drvdata->res_mem->start);
+ SSI_LOG_ERR("Couldn't allocate registers memory region at 0x%08X\n",
+ (unsigned int)new_drvdata->res_mem->start);
rc = -EBUSY;
goto init_cc_res_err;
}
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 1a405bb..3a734df 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -138,10 +138,9 @@ static int ssi_hash_map_result(struct device *dev,
digestsize);
return -ENOMEM;
}
- SSI_LOG_DEBUG("Mapped digest result buffer %u B "
- "at va=%pK to dma=%pad\n",
- digestsize, state->digest_result_buff,
- state->digest_result_dma_addr);
+ SSI_LOG_DEBUG("Mapped digest result buffer %u B at va=%pK to dma=%pad\n",
+ digestsize, state->digest_result_buff,
+ state->digest_result_dma_addr);
return 0;
}
@@ -352,11 +351,10 @@ static void ssi_hash_unmap_result(struct device *dev,
state->digest_result_dma_addr,
digestsize,
DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("unmpa digest result buffer "
- "va (%pK) pa (%pad) len %u\n",
- state->digest_result_buff,
- state->digest_result_dma_addr,
- digestsize);
+ SSI_LOG_DEBUG("unmpa digest result buffer va (%pK) pa (%pad) len %u\n",
+ state->digest_result_buff,
+ state->digest_result_dma_addr,
+ digestsize);
memcpy(result,
state->digest_result_buff,
digestsize);
@@ -994,13 +992,13 @@ static int ssi_hash_setkey(void *hash,
keylen, DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(&ctx->drvdata->plat_dev->dev,
ctx->key_params.key_dma_addr))) {
- SSI_LOG_ERR("Mapping key va=0x%p len=%u for"
- " DMA failed\n", key, keylen);
+ SSI_LOG_ERR("Mapping key va=0x%p len=%u for DMA failed\n",
+ key, keylen);
return -ENOMEM;
}
- SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad "
- "keylen=%u\n", ctx->key_params.key_dma_addr,
- ctx->key_params.keylen);
+ SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
+ ctx->key_params.key_dma_addr,
+ ctx->key_params.keylen);
if (keylen > blocksize) {
/* Load hash initial state */
@@ -1176,14 +1174,13 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
keylen, DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(&ctx->drvdata->plat_dev->dev,
ctx->key_params.key_dma_addr))) {
- SSI_LOG_ERR("Mapping key va=0x%p len=%u for"
- " DMA failed\n", key, keylen);
+ SSI_LOG_ERR("Mapping key va=0x%p len=%u for DMA failed\n",
+ key, keylen);
return -ENOMEM;
}
- SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad "
- "keylen=%u\n",
- ctx->key_params.key_dma_addr,
- ctx->key_params.keylen);
+ SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
+ ctx->key_params.key_dma_addr,
+ ctx->key_params.keylen);
ctx->is_hmac = true;
/* 1. Load the AES key */
@@ -1284,8 +1281,7 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx)
if (ctx->digest_buff_dma_addr != 0) {
dma_unmap_single(dev, ctx->digest_buff_dma_addr,
sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("Unmapped digest-buffer: "
- "digest_buff_dma_addr=%pad\n",
+ SSI_LOG_DEBUG("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n",
ctx->digest_buff_dma_addr);
ctx->digest_buff_dma_addr = 0;
}
@@ -1293,8 +1289,7 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx)
dma_unmap_single(dev, ctx->opad_tmp_keys_dma_addr,
sizeof(ctx->opad_tmp_keys_buff),
DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("Unmapped opad-digest: "
- "opad_tmp_keys_dma_addr=%pad\n",
+ SSI_LOG_DEBUG("Unmapped opad-digest: opad_tmp_keys_dma_addr=%pad\n",
ctx->opad_tmp_keys_dma_addr);
ctx->opad_tmp_keys_dma_addr = 0;
}
diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c
index 86364f8..bca44af 100644
--- a/drivers/staging/ccree/ssi_ivgen.c
+++ b/drivers/staging/ccree/ssi_ivgen.c
@@ -193,8 +193,8 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata)
/* Allocate "this" context */
drvdata->ivgen_handle = kzalloc(sizeof(struct ssi_ivgen_ctx), GFP_KERNEL);
if (!drvdata->ivgen_handle) {
- SSI_LOG_ERR("Not enough memory to allocate IVGEN context "
- "(%zu B)\n", sizeof(struct ssi_ivgen_ctx));
+ SSI_LOG_ERR("Not enough memory to allocate IVGEN context (%zu B)\n",
+ sizeof(struct ssi_ivgen_ctx));
rc = -ENOMEM;
goto out;
}
@@ -205,8 +205,8 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata)
&ivgen_ctx->pool_meta_dma,
GFP_KERNEL);
if (!ivgen_ctx->pool_meta) {
- SSI_LOG_ERR("Not enough memory to allocate DMA of pool_meta "
- "(%u B)\n", SSI_IVPOOL_META_SIZE);
+ SSI_LOG_ERR("Not enough memory to allocate DMA of pool_meta (%u B)\n",
+ SSI_IVPOOL_META_SIZE);
rc = -ENOMEM;
goto out;
}
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index 2eda82f..9a4bb5c 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -140,8 +140,8 @@ int request_mgr_init(struct ssi_drvdata *drvdata)
&req_mgr_h->dummy_comp_buff_dma,
GFP_KERNEL);
if (!req_mgr_h->dummy_comp_buff) {
- SSI_LOG_ERR("Not enough memory to allocate DMA (%zu) dropped "
- "buffer\n", sizeof(u32));
+ SSI_LOG_ERR("Not enough memory to allocate DMA (%zu) dropped buffer\n",
+ sizeof(u32));
rc = -ENOMEM;
goto req_mgr_init_err;
}
@@ -238,12 +238,9 @@ static inline int request_mgr_queues_status_check(
req_mgr_h->q_free_slots, total_seq_len);
}
/* No room in the HW queue try again later */
- SSI_LOG_DEBUG("HW FIFO full, timeout. req_queue_head=%d "
- "sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n",
- req_mgr_h->req_queue_head,
- MAX_REQUEST_QUEUE_SIZE,
- req_mgr_h->q_free_slots,
- total_seq_len);
+ SSI_LOG_DEBUG("HW FIFO full, timeout. req_queue_head=%d sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n",
+ req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE,
+ req_mgr_h->q_free_slots, total_seq_len);
return -EAGAIN;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 02/22] staging: ccree: kmalloc by sizeof var not type
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 01/22] staging: ccree: fix split strings Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 03/22] staging: ccree: Replace kzalloc with devm_kzalloc Gilad Ben-Yossef
` (20 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Change places where we alloc memory by sizeof type to sizeof var.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_aead.c | 4 ++--
drivers/staging/ccree/ssi_cipher.c | 4 ++--
drivers/staging/ccree/ssi_driver.c | 2 +-
drivers/staging/ccree/ssi_hash.c | 4 ++--
drivers/staging/ccree/ssi_ivgen.c | 2 +-
drivers/staging/ccree/ssi_request_mgr.c | 2 +-
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index d8f2249..a8cb432 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -2658,7 +2658,7 @@ static struct ssi_crypto_alg *ssi_aead_create_alg(struct ssi_alg_template *templ
struct ssi_crypto_alg *t_alg;
struct aead_alg *alg;
- t_alg = kzalloc(sizeof(struct ssi_crypto_alg), GFP_KERNEL);
+ t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
if (!t_alg) {
SSI_LOG_ERR("failed to allocate t_alg\n");
return ERR_PTR(-ENOMEM);
@@ -2713,7 +2713,7 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata)
int rc = -ENOMEM;
int alg;
- aead_handle = kmalloc(sizeof(struct ssi_aead_handle), GFP_KERNEL);
+ aead_handle = kmalloc(sizeof(*aead_handle), GFP_KERNEL);
if (!aead_handle) {
rc = -ENOMEM;
goto fail0;
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index 068b10b..d98178d 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -1215,7 +1215,7 @@ struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template *templa
struct ssi_crypto_alg *t_alg;
struct crypto_alg *alg;
- t_alg = kzalloc(sizeof(struct ssi_crypto_alg), GFP_KERNEL);
+ t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
if (!t_alg) {
SSI_LOG_ERR("failed to allocate t_alg\n");
return ERR_PTR(-ENOMEM);
@@ -1276,7 +1276,7 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata)
int rc = -ENOMEM;
int alg;
- ablkcipher_handle = kmalloc(sizeof(struct ssi_blkcipher_handle),
+ ablkcipher_handle = kmalloc(sizeof(*ablkcipher_handle),
GFP_KERNEL);
if (!ablkcipher_handle)
return -ENOMEM;
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index d104dbd..1cae2b7 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -223,7 +223,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
struct resource *req_mem_cc_regs = NULL;
void __iomem *cc_base = NULL;
bool irq_registered = false;
- struct ssi_drvdata *new_drvdata = kzalloc(sizeof(struct ssi_drvdata), GFP_KERNEL);
+ struct ssi_drvdata *new_drvdata = kzalloc(sizeof(*new_drvdata), GFP_KERNEL);
struct device *dev = &plat_dev->dev;
struct device_node *np = dev->of_node;
u32 signature_val;
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 3a734df..6c08b1d 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -2055,7 +2055,7 @@ ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed)
struct crypto_alg *alg;
struct ahash_alg *halg;
- t_crypto_alg = kzalloc(sizeof(struct ssi_hash_alg), GFP_KERNEL);
+ t_crypto_alg = kzalloc(sizeof(*t_crypto_alg), GFP_KERNEL);
if (!t_crypto_alg) {
SSI_LOG_ERR("failed to allocate t_alg\n");
return ERR_PTR(-ENOMEM);
@@ -2221,7 +2221,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata)
int rc = 0;
int alg;
- hash_handle = kzalloc(sizeof(struct ssi_hash_handle), GFP_KERNEL);
+ hash_handle = kzalloc(sizeof(*hash_handle), GFP_KERNEL);
if (!hash_handle) {
SSI_LOG_ERR("kzalloc failed to allocate %zu B\n",
sizeof(struct ssi_hash_handle));
diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c
index bca44af..93a2a94 100644
--- a/drivers/staging/ccree/ssi_ivgen.c
+++ b/drivers/staging/ccree/ssi_ivgen.c
@@ -191,7 +191,7 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata)
int rc;
/* Allocate "this" context */
- drvdata->ivgen_handle = kzalloc(sizeof(struct ssi_ivgen_ctx), GFP_KERNEL);
+ drvdata->ivgen_handle = kzalloc(sizeof(*drvdata->ivgen_handle), GFP_KERNEL);
if (!drvdata->ivgen_handle) {
SSI_LOG_ERR("Not enough memory to allocate IVGEN context (%zu B)\n",
sizeof(struct ssi_ivgen_ctx));
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index 9a4bb5c..cae9904 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -100,7 +100,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata)
struct ssi_request_mgr_handle *req_mgr_h;
int rc = 0;
- req_mgr_h = kzalloc(sizeof(struct ssi_request_mgr_handle), GFP_KERNEL);
+ req_mgr_h = kzalloc(sizeof(*req_mgr_h), GFP_KERNEL);
if (!req_mgr_h) {
rc = -ENOMEM;
goto req_mgr_init_err;
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 03/22] staging: ccree: Replace kzalloc with devm_kzalloc
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 01/22] staging: ccree: fix split strings Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 02/22] staging: ccree: kmalloc by sizeof var not type Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 04/22] staging: ccree: Convert to devm_ioremap_resource for map, unmap Gilad Ben-Yossef
` (19 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang, Suniel Mahesh
From: Suniel Mahesh <sunil.m@techveda.org>
It is recommended to use managed function devm_kzalloc, which
simplifies driver cleanup paths and driver code.
This patch does the following:
(a) replace kzalloc with devm_kzalloc.
(b) drop kfree(), because memory allocated with devm_kzalloc() is
automatically freed on driver detach, otherwise it leads to a double
free.
(c) remove unnecessary blank lines.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
[gby: rebase on top of latest coding style fixes changes]
Acked-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_driver.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 1cae2b7..97dfc2c 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -223,13 +223,15 @@ static int init_cc_resources(struct platform_device *plat_dev)
struct resource *req_mem_cc_regs = NULL;
void __iomem *cc_base = NULL;
bool irq_registered = false;
- struct ssi_drvdata *new_drvdata = kzalloc(sizeof(*new_drvdata), GFP_KERNEL);
+ struct ssi_drvdata *new_drvdata;
struct device *dev = &plat_dev->dev;
struct device_node *np = dev->of_node;
u32 signature_val;
int rc = 0;
- if (unlikely(!new_drvdata)) {
+ new_drvdata = devm_kzalloc(&plat_dev->dev, sizeof(*new_drvdata),
+ GFP_KERNEL);
+ if (!new_drvdata) {
SSI_LOG_ERR("Failed to allocate drvdata");
rc = -ENOMEM;
goto init_cc_res_err;
@@ -434,10 +436,8 @@ static int init_cc_resources(struct platform_device *plat_dev)
resource_size(new_drvdata->res_mem));
new_drvdata->res_mem = NULL;
}
- kfree(new_drvdata);
dev_set_drvdata(&plat_dev->dev, NULL);
}
-
return rc;
}
@@ -478,8 +478,6 @@ static void cleanup_cc_resources(struct platform_device *plat_dev)
drvdata->cc_base = NULL;
drvdata->res_mem = NULL;
}
-
- kfree(drvdata);
dev_set_drvdata(&plat_dev->dev, NULL);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 04/22] staging: ccree: Convert to devm_ioremap_resource for map, unmap
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (2 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 03/22] staging: ccree: Replace kzalloc with devm_kzalloc Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 05/22] staging: ccree: Use platform_get_irq and devm_request_irq Gilad Ben-Yossef
` (18 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang, Suniel Mahesh
From: Suniel Mahesh <sunil.m@techveda.org>
It is recommended to use managed function devm_ioremap_resource(),
which simplifies driver cleanup paths and driver code.
This patch does the following:
(a) replace request_mem_region(), ioremap() and corresponding error
handling with devm_ioremap_resource().
(b) remove struct resource pointer(res_mem) in struct ssi_drvdata as it
seems redundant, use struct resource pointer which is defined locally and
adjust return value of platform_get_resource() accordingly.
(c) release_mem_region() and iounmap() are dropped, since devm_ioremap_
resource() releases and unmaps mem region on driver detach.
(d) adjust log messages accordingly and remove any blank lines.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
[gby: rebase on top of latest coding style fixes changes]
Acked-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_driver.c | 60 ++++++++++----------------------------
drivers/staging/ccree/ssi_driver.h | 1 -
2 files changed, 15 insertions(+), 46 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 97dfc2c..603eb03 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -246,35 +246,21 @@ static int init_cc_resources(struct platform_device *plat_dev)
dev_set_drvdata(&plat_dev->dev, new_drvdata);
/* Get device resources */
/* First CC registers space */
- new_drvdata->res_mem = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
- if (unlikely(!new_drvdata->res_mem)) {
- SSI_LOG_ERR("Failed getting IO memory resource\n");
- rc = -ENODEV;
- goto init_cc_res_err;
- }
- SSI_LOG_DEBUG("Got MEM resource (%s): start=%pad end=%pad\n",
- new_drvdata->res_mem->name,
- new_drvdata->res_mem->start,
- new_drvdata->res_mem->end);
+ req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
/* Map registers space */
- req_mem_cc_regs = request_mem_region(new_drvdata->res_mem->start, resource_size(new_drvdata->res_mem), "arm_cc7x_regs");
- if (unlikely(!req_mem_cc_regs)) {
- SSI_LOG_ERR("Couldn't allocate registers memory region at 0x%08X\n",
- (unsigned int)new_drvdata->res_mem->start);
- rc = -EBUSY;
- goto init_cc_res_err;
- }
- cc_base = ioremap(new_drvdata->res_mem->start, resource_size(new_drvdata->res_mem));
- if (unlikely(!cc_base)) {
- SSI_LOG_ERR("ioremap[CC](0x%08X,0x%08X) failed\n",
- (unsigned int)new_drvdata->res_mem->start,
- (unsigned int)resource_size(new_drvdata->res_mem));
- rc = -ENOMEM;
+ new_drvdata->cc_base = devm_ioremap_resource(&plat_dev->dev,
+ req_mem_cc_regs);
+ if (IS_ERR(new_drvdata->cc_base)) {
+ rc = PTR_ERR(new_drvdata->cc_base);
goto init_cc_res_err;
}
- SSI_LOG_DEBUG("CC registers mapped from %pa to 0x%p\n", &new_drvdata->res_mem->start, cc_base);
- new_drvdata->cc_base = cc_base;
-
+ SSI_LOG_DEBUG("Got MEM resource (%s): start=%pad end=%pad\n",
+ req_mem_cc_regs->name,
+ req_mem_cc_regs->start,
+ req_mem_cc_regs->end);
+ SSI_LOG_DEBUG("CC registers mapped from %pa to 0x%p\n",
+ &req_mem_cc_regs->start, new_drvdata->cc_base);
+ cc_base = new_drvdata->cc_base;
/* Then IRQ */
new_drvdata->res_irq = platform_get_resource(plat_dev, IORESOURCE_IRQ, 0);
if (unlikely(!new_drvdata->res_irq)) {
@@ -424,17 +410,9 @@ static int init_cc_resources(struct platform_device *plat_dev)
#ifdef ENABLE_CC_SYSFS
ssi_sysfs_fini();
#endif
-
- if (req_mem_cc_regs) {
- if (irq_registered) {
- free_irq(new_drvdata->res_irq->start, new_drvdata);
- new_drvdata->res_irq = NULL;
- iounmap(cc_base);
- new_drvdata->cc_base = NULL;
- }
- release_mem_region(new_drvdata->res_mem->start,
- resource_size(new_drvdata->res_mem));
- new_drvdata->res_mem = NULL;
+ if (irq_registered) {
+ free_irq(new_drvdata->res_irq->start, new_drvdata);
+ new_drvdata->res_irq = NULL;
}
dev_set_drvdata(&plat_dev->dev, NULL);
}
@@ -470,14 +448,6 @@ static void cleanup_cc_resources(struct platform_device *plat_dev)
cc_clk_off(drvdata);
free_irq(drvdata->res_irq->start, drvdata);
drvdata->res_irq = NULL;
-
- if (drvdata->cc_base) {
- iounmap(drvdata->cc_base);
- release_mem_region(drvdata->res_mem->start,
- resource_size(drvdata->res_mem));
- drvdata->cc_base = NULL;
- drvdata->res_mem = NULL;
- }
dev_set_drvdata(&plat_dev->dev, NULL);
}
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index b6ad89a..518c0bf 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -128,7 +128,6 @@ struct ssi_crypto_req {
* @fw_ver: SeP loaded firmware version
*/
struct ssi_drvdata {
- struct resource *res_mem;
struct resource *res_irq;
void __iomem *cc_base;
unsigned int irq;
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 05/22] staging: ccree: Use platform_get_irq and devm_request_irq
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (3 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 04/22] staging: ccree: Convert to devm_ioremap_resource for map, unmap Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 06/22] staging: ccree: simplify resource release on error Gilad Ben-Yossef
` (17 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang, Suniel Mahesh
From: Suniel Mahesh <sunil.m@techveda.org>
It is recommended to use managed function devm_request_irq(),
which simplifies driver cleanup paths and driver code.
This patch does the following:
(a) replace platform_get_resource(), request_irq() and corresponding
error handling with platform_get_irq() and devm_request_irq().
(b) remove struct resource pointer(res_irq) in struct ssi_drvdata as
it seems redundant.
(c) change type of member irq in struct ssi_drvdata from unsigned int
to int, as return type of platform_get_irq is int and can be used in
error handling.
(d) remove irq_registered variable from driver probe as it seems
redundant.
(e) free_irq is not required any more, devm_request_irq() free's it
on driver detach.
(f) adjust log messages accordingly and remove any blank lines.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Acked-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_driver.c | 30 +++++++++---------------------
drivers/staging/ccree/ssi_driver.h | 3 +--
2 files changed, 10 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 603eb03..c18e7e3 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -222,7 +222,6 @@ static int init_cc_resources(struct platform_device *plat_dev)
{
struct resource *req_mem_cc_regs = NULL;
void __iomem *cc_base = NULL;
- bool irq_registered = false;
struct ssi_drvdata *new_drvdata;
struct device *dev = &plat_dev->dev;
struct device_node *np = dev->of_node;
@@ -262,26 +261,22 @@ static int init_cc_resources(struct platform_device *plat_dev)
&req_mem_cc_regs->start, new_drvdata->cc_base);
cc_base = new_drvdata->cc_base;
/* Then IRQ */
- new_drvdata->res_irq = platform_get_resource(plat_dev, IORESOURCE_IRQ, 0);
- if (unlikely(!new_drvdata->res_irq)) {
+ new_drvdata->irq = platform_get_irq(plat_dev, 0);
+ if (new_drvdata->irq < 0) {
SSI_LOG_ERR("Failed getting IRQ resource\n");
- rc = -ENODEV;
+ rc = new_drvdata->irq;
goto init_cc_res_err;
}
- rc = request_irq(new_drvdata->res_irq->start, cc_isr,
- IRQF_SHARED, "arm_cc7x", new_drvdata);
- if (unlikely(rc != 0)) {
- SSI_LOG_ERR("Could not register to interrupt %llu\n",
- (unsigned long long)new_drvdata->res_irq->start);
+ rc = devm_request_irq(&plat_dev->dev, new_drvdata->irq, cc_isr,
+ IRQF_SHARED, "arm_cc7x", new_drvdata);
+ if (rc) {
+ SSI_LOG_ERR("Could not register to interrupt %d\n",
+ new_drvdata->irq);
goto init_cc_res_err;
}
init_completion(&new_drvdata->icache_setup_completion);
- irq_registered = true;
- SSI_LOG_DEBUG("Registered to IRQ (%s) %llu\n",
- new_drvdata->res_irq->name,
- (unsigned long long)new_drvdata->res_irq->start);
-
+ SSI_LOG_DEBUG("Registered to IRQ: %d\n", new_drvdata->irq);
new_drvdata->plat_dev = plat_dev;
rc = cc_clk_on(new_drvdata);
@@ -410,10 +405,6 @@ static int init_cc_resources(struct platform_device *plat_dev)
#ifdef ENABLE_CC_SYSFS
ssi_sysfs_fini();
#endif
- if (irq_registered) {
- free_irq(new_drvdata->res_irq->start, new_drvdata);
- new_drvdata->res_irq = NULL;
- }
dev_set_drvdata(&plat_dev->dev, NULL);
}
return rc;
@@ -443,11 +434,8 @@ static void cleanup_cc_resources(struct platform_device *plat_dev)
#ifdef ENABLE_CC_SYSFS
ssi_sysfs_fini();
#endif
-
fini_cc_regs(drvdata);
cc_clk_off(drvdata);
- free_irq(drvdata->res_irq->start, drvdata);
- drvdata->res_irq = NULL;
dev_set_drvdata(&plat_dev->dev, NULL);
}
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index 518c0bf..88ef370 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -128,9 +128,8 @@ struct ssi_crypto_req {
* @fw_ver: SeP loaded firmware version
*/
struct ssi_drvdata {
- struct resource *res_irq;
void __iomem *cc_base;
- unsigned int irq;
+ int irq;
u32 irq_mask;
u32 fw_ver;
/* Calibration time of start/stop
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 06/22] staging: ccree: simplify resource release on error
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (4 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 05/22] staging: ccree: Use platform_get_irq and devm_request_irq Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 07/22] staging: ccree: remove unused completion Gilad Ben-Yossef
` (16 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
The resource release on probe/init error was being handled
in an awkward manner and possibly leaking memory on certain
(unlikely) error path.
Fix it by simplifying the error resource release and making
it easier to track.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_aead.c | 3 +-
drivers/staging/ccree/ssi_cipher.c | 3 +-
drivers/staging/ccree/ssi_driver.c | 102 ++++++++++++++++++++-----------------
drivers/staging/ccree/ssi_hash.c | 3 +-
4 files changed, 59 insertions(+), 52 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index a8cb432..66eedbe 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -2719,6 +2719,7 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata)
goto fail0;
}
+ INIT_LIST_HEAD(&aead_handle->aead_list);
drvdata->aead_handle = aead_handle;
aead_handle->sram_workspace_addr = ssi_sram_mgr_alloc(
@@ -2729,8 +2730,6 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata)
goto fail1;
}
- INIT_LIST_HEAD(&aead_handle->aead_list);
-
/* Linux crypto */
for (alg = 0; alg < ARRAY_SIZE(aead_algs); alg++) {
t_alg = ssi_aead_create_alg(&aead_algs[alg]);
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index d98178d..712b21d 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -1281,9 +1281,8 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata)
if (!ablkcipher_handle)
return -ENOMEM;
- drvdata->blkcipher_handle = ablkcipher_handle;
-
INIT_LIST_HEAD(&ablkcipher_handle->blkcipher_alg_list);
+ drvdata->blkcipher_handle = ablkcipher_handle;
/* Linux crypto */
SSI_LOG_DEBUG("Number of algorithms = %zu\n", ARRAY_SIZE(blkcipher_algs));
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index c18e7e3..1b95f90 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -233,16 +233,14 @@ static int init_cc_resources(struct platform_device *plat_dev)
if (!new_drvdata) {
SSI_LOG_ERR("Failed to allocate drvdata");
rc = -ENOMEM;
- goto init_cc_res_err;
+ goto post_drvdata_err;
}
+ dev_set_drvdata(&plat_dev->dev, new_drvdata);
+ new_drvdata->plat_dev = plat_dev;
new_drvdata->clk = of_clk_get(np, 0);
new_drvdata->coherent = of_dma_is_coherent(np);
- /*Initialize inflight counter used in dx_ablkcipher_secure_complete used for count of BYSPASS blocks operations*/
- new_drvdata->inflight_counter = 0;
-
- dev_set_drvdata(&plat_dev->dev, new_drvdata);
/* Get device resources */
/* First CC registers space */
req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
@@ -250,38 +248,42 @@ static int init_cc_resources(struct platform_device *plat_dev)
new_drvdata->cc_base = devm_ioremap_resource(&plat_dev->dev,
req_mem_cc_regs);
if (IS_ERR(new_drvdata->cc_base)) {
+ SSI_LOG_ERR("Failed to ioremap registers");
rc = PTR_ERR(new_drvdata->cc_base);
- goto init_cc_res_err;
+ goto post_drvdata_err;
}
+
SSI_LOG_DEBUG("Got MEM resource (%s): start=%pad end=%pad\n",
req_mem_cc_regs->name,
req_mem_cc_regs->start,
req_mem_cc_regs->end);
SSI_LOG_DEBUG("CC registers mapped from %pa to 0x%p\n",
&req_mem_cc_regs->start, new_drvdata->cc_base);
+
cc_base = new_drvdata->cc_base;
+
/* Then IRQ */
new_drvdata->irq = platform_get_irq(plat_dev, 0);
if (new_drvdata->irq < 0) {
SSI_LOG_ERR("Failed getting IRQ resource\n");
rc = new_drvdata->irq;
- goto init_cc_res_err;
+ goto post_drvdata_err;
}
+
rc = devm_request_irq(&plat_dev->dev, new_drvdata->irq, cc_isr,
IRQF_SHARED, "arm_cc7x", new_drvdata);
if (rc) {
SSI_LOG_ERR("Could not register to interrupt %d\n",
new_drvdata->irq);
- goto init_cc_res_err;
+ goto post_drvdata_err;
}
- init_completion(&new_drvdata->icache_setup_completion);
-
SSI_LOG_DEBUG("Registered to IRQ: %d\n", new_drvdata->irq);
- new_drvdata->plat_dev = plat_dev;
+
+ init_completion(&new_drvdata->icache_setup_completion);
rc = cc_clk_on(new_drvdata);
if (rc)
- goto init_cc_res_err;
+ goto post_drvdata_err;
if (!new_drvdata->plat_dev->dev.dma_mask)
new_drvdata->plat_dev->dev.dma_mask = &new_drvdata->plat_dev->dev.coherent_dma_mask;
@@ -295,7 +297,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
SSI_LOG_ERR("Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
signature_val, (u32)DX_DEV_SIGNATURE);
rc = -EINVAL;
- goto init_cc_res_err;
+ goto post_clk_err;
}
SSI_LOG_DEBUG("CC SIGNATURE=0x%08X\n", signature_val);
@@ -306,21 +308,26 @@ static int init_cc_resources(struct platform_device *plat_dev)
rc = init_cc_regs(new_drvdata, true);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("init_cc_regs failed\n");
- goto init_cc_res_err;
+ goto post_clk_err;
}
#ifdef ENABLE_CC_SYSFS
rc = ssi_sysfs_init(&plat_dev->dev.kobj, new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("init_stat_db failed\n");
- goto init_cc_res_err;
+ goto post_regs_err;
}
#endif
+ rc = ssi_fips_init(new_drvdata);
+ if (unlikely(rc != 0)) {
+ SSI_LOG_ERR("SSI_FIPS_INIT failed 0x%x\n", rc);
+ goto post_sysfs_err;
+ }
rc = ssi_sram_mgr_init(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("ssi_sram_mgr_init failed\n");
- goto init_cc_res_err;
+ goto post_fips_init_err;
}
new_drvdata->mlli_sram_addr =
@@ -328,57 +335,51 @@ static int init_cc_resources(struct platform_device *plat_dev)
if (unlikely(new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR)) {
SSI_LOG_ERR("Failed to alloc MLLI Sram buffer\n");
rc = -ENOMEM;
- goto init_cc_res_err;
+ goto post_sram_mgr_err;
}
rc = request_mgr_init(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("request_mgr_init failed\n");
- goto init_cc_res_err;
+ goto post_sram_mgr_err;
}
rc = ssi_buffer_mgr_init(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("buffer_mgr_init failed\n");
- goto init_cc_res_err;
+ goto post_req_mgr_err;
}
rc = ssi_power_mgr_init(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("ssi_power_mgr_init failed\n");
- goto init_cc_res_err;
- }
-
- rc = ssi_fips_init(new_drvdata);
- if (unlikely(rc != 0)) {
- SSI_LOG_ERR("SSI_FIPS_INIT failed 0x%x\n", rc);
- goto init_cc_res_err;
+ goto post_buf_mgr_err;
}
rc = ssi_ivgen_init(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("ssi_ivgen_init failed\n");
- goto init_cc_res_err;
+ goto post_power_mgr_err;
}
/* Allocate crypto algs */
rc = ssi_ablkcipher_alloc(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("ssi_ablkcipher_alloc failed\n");
- goto init_cc_res_err;
+ goto post_ivgen_err;
}
/* hash must be allocated before aead since hash exports APIs */
rc = ssi_hash_alloc(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("ssi_hash_alloc failed\n");
- goto init_cc_res_err;
+ goto post_cipher_err;
}
rc = ssi_aead_alloc(new_drvdata);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("ssi_aead_alloc failed\n");
- goto init_cc_res_err;
+ goto post_hash_err;
}
/* If we got here and FIPS mode is enabled
@@ -389,24 +390,33 @@ static int init_cc_resources(struct platform_device *plat_dev)
return 0;
-init_cc_res_err:
- SSI_LOG_ERR("Freeing CC HW resources!\n");
-
- if (new_drvdata) {
- ssi_aead_free(new_drvdata);
- ssi_hash_free(new_drvdata);
- ssi_ablkcipher_free(new_drvdata);
- ssi_ivgen_fini(new_drvdata);
- ssi_power_mgr_fini(new_drvdata);
- ssi_buffer_mgr_fini(new_drvdata);
- request_mgr_fini(new_drvdata);
- ssi_sram_mgr_fini(new_drvdata);
- ssi_fips_fini(new_drvdata);
+post_hash_err:
+ ssi_hash_free(new_drvdata);
+post_cipher_err:
+ ssi_ablkcipher_free(new_drvdata);
+post_ivgen_err:
+ ssi_ivgen_fini(new_drvdata);
+post_power_mgr_err:
+ ssi_power_mgr_fini(new_drvdata);
+post_buf_mgr_err:
+ ssi_buffer_mgr_fini(new_drvdata);
+post_req_mgr_err:
+ request_mgr_fini(new_drvdata);
+post_sram_mgr_err:
+ ssi_sram_mgr_fini(new_drvdata);
+post_fips_init_err:
+ ssi_fips_fini(new_drvdata);
+post_sysfs_err:
#ifdef ENABLE_CC_SYSFS
- ssi_sysfs_fini();
+ ssi_sysfs_fini();
#endif
- dev_set_drvdata(&plat_dev->dev, NULL);
- }
+post_regs_err:
+ fini_cc_regs(new_drvdata);
+post_clk_err:
+ cc_clk_off(new_drvdata);
+post_drvdata_err:
+ SSI_LOG_ERR("ccree init error occurred!\n");
+ dev_set_drvdata(&plat_dev->dev, NULL);
return rc;
}
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 6c08b1d..3e7873c 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -2229,6 +2229,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata)
goto fail;
}
+ INIT_LIST_HEAD(&hash_handle->hash_list);
drvdata->hash_handle = hash_handle;
sram_size_to_alloc = sizeof(digest_len_init) +
@@ -2259,8 +2260,6 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata)
goto fail;
}
- INIT_LIST_HEAD(&hash_handle->hash_list);
-
/* ahash registration */
for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) {
struct ssi_hash_alg *t_alg;
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 07/22] staging: ccree: remove unused completion
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (5 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 06/22] staging: ccree: simplify resource release on error Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 08/22] staging: ccree: remove m32r as supported platform Gilad Ben-Yossef
` (15 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
icache_setup_completion is no longer used. Remove it.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_driver.c | 2 --
drivers/staging/ccree/ssi_driver.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 1b95f90..928c988 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -279,8 +279,6 @@ static int init_cc_resources(struct platform_device *plat_dev)
}
SSI_LOG_DEBUG("Registered to IRQ: %d\n", new_drvdata->irq);
- init_completion(&new_drvdata->icache_setup_completion);
-
rc = cc_clk_on(new_drvdata);
if (rc)
goto post_drvdata_err;
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index 88ef370..9b6476d 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -138,7 +138,6 @@ struct ssi_drvdata {
u32 monitor_null_cycles;
struct platform_device *plat_dev;
ssi_sram_addr_t mlli_sram_addr;
- struct completion icache_setup_completion;
void *buff_mgr_handle;
void *hash_handle;
void *aead_handle;
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 08/22] staging: ccree: remove m32r as supported platform
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (6 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 07/22] staging: ccree: remove unused completion Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 09/22] staging: ccree: Fix format/argument mismatches Gilad Ben-Yossef
` (14 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
M32R requires special handling due due to how it has implemented
ioread32. It is also an orphaned arch on Linux and doesn't seem
to be worth the trouble. So until we have a real user, remove
support for it.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/ccree/Kconfig b/drivers/staging/ccree/Kconfig
index 0b3092b..89af1c5 100644
--- a/drivers/staging/ccree/Kconfig
+++ b/drivers/staging/ccree/Kconfig
@@ -1,6 +1,6 @@
config CRYPTO_DEV_CCREE
tristate "Support for ARM TrustZone CryptoCell C7XX family of Crypto accelerators"
- depends on CRYPTO && CRYPTO_HW && OF && HAS_DMA
+ depends on CRYPTO && CRYPTO_HW && OF && HAS_DMA && !M32R
default n
select CRYPTO_HASH
select CRYPTO_BLKCIPHER
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 09/22] staging: ccree: Fix format/argument mismatches
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (7 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 08/22] staging: ccree: remove m32r as supported platform Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 10/22] staging: ccree: rewrite GET_DMA_BUFFER_TYPE as func Gilad Ben-Yossef
` (13 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang, Joe Perches
From: Joe Perches <joe@perches.com>
By default, debug logging is disabled by CC_DEBUG not being defined.
Convert SSI_LOG_DEBUG to use no_printk instead of an empty define
to validate formats and arguments.
Fix fallout.
Miscellanea:
o One of the conversions now uses %pR instead of multiple uses of %pad
Signed-off-by: Joe Perches <joe@perches.com>
[ gby: rebase on top of latest changes ]
Acked-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_aead.c | 8 ++++----
drivers/staging/ccree/ssi_buffer_mgr.c | 29 +++++++++++++---------------
drivers/staging/ccree/ssi_cipher.c | 10 +++++-----
drivers/staging/ccree/ssi_driver.c | 10 ++++------
drivers/staging/ccree/ssi_driver.h | 2 +-
drivers/staging/ccree/ssi_hash.c | 34 ++++++++++++++++-----------------
drivers/staging/ccree/ssi_request_mgr.c | 6 +++---
7 files changed, 47 insertions(+), 52 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 66eedbe..03533c8 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -103,7 +103,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
if (ctx->enckey) {
dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, ctx->enckey_dma_addr);
SSI_LOG_DEBUG("Freed enckey DMA buffer enckey_dma_addr=%pad\n",
- ctx->enckey_dma_addr);
+ &ctx->enckey_dma_addr);
ctx->enckey_dma_addr = 0;
ctx->enckey = NULL;
}
@@ -117,7 +117,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
xcbc->xcbc_keys_dma_addr);
}
SSI_LOG_DEBUG("Freed xcbc_keys DMA buffer xcbc_keys_dma_addr=%pad\n",
- xcbc->xcbc_keys_dma_addr);
+ &xcbc->xcbc_keys_dma_addr);
xcbc->xcbc_keys_dma_addr = 0;
xcbc->xcbc_keys = NULL;
} else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */
@@ -128,7 +128,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
hmac->ipad_opad,
hmac->ipad_opad_dma_addr);
SSI_LOG_DEBUG("Freed ipad_opad DMA buffer ipad_opad_dma_addr=%pad\n",
- hmac->ipad_opad_dma_addr);
+ &hmac->ipad_opad_dma_addr);
hmac->ipad_opad_dma_addr = 0;
hmac->ipad_opad = NULL;
}
@@ -137,7 +137,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
hmac->padded_authkey,
hmac->padded_authkey_dma_addr);
SSI_LOG_DEBUG("Freed padded_authkey DMA buffer padded_authkey_dma_addr=%pad\n",
- hmac->padded_authkey_dma_addr);
+ &hmac->padded_authkey_dma_addr);
hmac->padded_authkey_dma_addr = 0;
hmac->padded_authkey = NULL;
}
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c
index d7ce293..0b81fd5 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -14,6 +14,7 @@
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/kernel.h>
#include <linux/crypto.h>
#include <linux/version.h>
#include <crypto/algapi.h>
@@ -33,14 +34,10 @@
#include "ssi_hash.h"
#include "ssi_aead.h"
-#ifdef CC_DEBUG
#define GET_DMA_BUFFER_TYPE(buff_type) ( \
((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \
((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \
((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID")
-#else
-#define GET_DMA_BUFFER_TYPE(buff_type)
-#endif
enum dma_buffer_type {
DMA_NULL_TYPE = -1,
@@ -260,7 +257,7 @@ static int ssi_buffer_mgr_generate_mlli(
mlli_params->mlli_len = (total_nents * LLI_ENTRY_BYTE_SIZE);
SSI_LOG_DEBUG("MLLI params: virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n",
- mlli_params->mlli_virt_addr, mlli_params->mlli_dma_addr,
+ mlli_params->mlli_virt_addr, &mlli_params->mlli_dma_addr,
mlli_params->mlli_len);
build_mlli_exit:
@@ -275,7 +272,7 @@ static inline void ssi_buffer_mgr_add_buffer_entry(
unsigned int index = sgl_data->num_of_buffers;
SSI_LOG_DEBUG("index=%u single_buff=%pad buffer_len=0x%08X is_last=%d\n",
- index, buffer_dma, buffer_len, is_last_entry);
+ index, &buffer_dma, buffer_len, is_last_entry);
sgl_data->nents[index] = 1;
sgl_data->entry[index].buffer_dma = buffer_dma;
sgl_data->offset[index] = 0;
@@ -358,7 +355,7 @@ static int ssi_buffer_mgr_map_scatterlist(
}
SSI_LOG_DEBUG("Mapped sg: dma_address=%pad page=%p addr=%pK offset=%u "
"length=%u\n",
- sg_dma_address(sg),
+ &sg_dma_address(sg),
sg_page(sg),
sg_virt(sg),
sg->offset, sg->length);
@@ -420,7 +417,7 @@ ssi_aead_handle_config_buf(struct device *dev,
}
SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad page=%p addr=%pK "
"offset=%u length=%u\n",
- sg_dma_address(&areq_ctx->ccm_adata_sg),
+ &sg_dma_address(&areq_ctx->ccm_adata_sg),
sg_page(&areq_ctx->ccm_adata_sg),
sg_virt(&areq_ctx->ccm_adata_sg),
areq_ctx->ccm_adata_sg.offset,
@@ -451,7 +448,7 @@ static inline int ssi_ahash_handle_curr_buf(struct device *dev,
}
SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad page=%p addr=%pK "
"offset=%u length=%u\n",
- sg_dma_address(areq_ctx->buff_sg),
+ &sg_dma_address(areq_ctx->buff_sg),
sg_page(areq_ctx->buff_sg),
sg_virt(areq_ctx->buff_sg),
areq_ctx->buff_sg->offset,
@@ -476,7 +473,7 @@ void ssi_buffer_mgr_unmap_blkcipher_request(
if (likely(req_ctx->gen_ctx.iv_dma_addr != 0)) {
SSI_LOG_DEBUG("Unmapped iv: iv_dma_addr=%pad iv_size=%u\n",
- req_ctx->gen_ctx.iv_dma_addr,
+ &req_ctx->gen_ctx.iv_dma_addr,
ivsize);
dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr,
ivsize,
@@ -537,7 +534,7 @@ int ssi_buffer_mgr_map_blkcipher_request(
}
SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=%pad\n",
ivsize, info,
- req_ctx->gen_ctx.iv_dma_addr);
+ &req_ctx->gen_ctx.iv_dma_addr);
} else {
req_ctx->gen_ctx.iv_dma_addr = 0;
}
@@ -667,7 +664,7 @@ void ssi_buffer_mgr_unmap_aead_request(
*/
if (areq_ctx->mlli_params.curr_pool) {
SSI_LOG_DEBUG("free MLLI buffer: dma=%pad virt=%pK\n",
- areq_ctx->mlli_params.mlli_dma_addr,
+ &areq_ctx->mlli_params.mlli_dma_addr,
areq_ctx->mlli_params.mlli_virt_addr);
dma_pool_free(areq_ctx->mlli_params.curr_pool,
areq_ctx->mlli_params.mlli_virt_addr,
@@ -786,7 +783,7 @@ static inline int ssi_buffer_mgr_aead_chain_iv(
SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=%pad\n",
hw_iv_size, req->iv,
- areq_ctx->gen_ctx.iv_dma_addr);
+ &areq_ctx->gen_ctx.iv_dma_addr);
if (do_chain && areq_ctx->plaintext_authenticate_only) { // TODO: what about CTR?? ask Ron
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
unsigned int iv_size_to_authenc = crypto_aead_ivsize(tfm);
@@ -1711,7 +1708,7 @@ void ssi_buffer_mgr_unmap_hash_request(
*/
if (areq_ctx->mlli_params.curr_pool) {
SSI_LOG_DEBUG("free MLLI buffer: dma=%pad virt=%pK\n",
- areq_ctx->mlli_params.mlli_dma_addr,
+ &areq_ctx->mlli_params.mlli_dma_addr,
areq_ctx->mlli_params.mlli_virt_addr);
dma_pool_free(areq_ctx->mlli_params.curr_pool,
areq_ctx->mlli_params.mlli_virt_addr,
@@ -1721,7 +1718,7 @@ void ssi_buffer_mgr_unmap_hash_request(
if ((src) && likely(areq_ctx->in_nents != 0)) {
SSI_LOG_DEBUG("Unmapped sg src: virt=%pK dma=%pad len=0x%X\n",
sg_virt(src),
- sg_dma_address(src),
+ &sg_dma_address(src),
sg_dma_len(src));
dma_unmap_sg(dev, src,
areq_ctx->in_nents, DMA_TO_DEVICE);
@@ -1730,7 +1727,7 @@ void ssi_buffer_mgr_unmap_hash_request(
if (*prev_len != 0) {
SSI_LOG_DEBUG("Unmapped buffer: areq_ctx->buff_sg=%pK dma=%pad len 0x%X\n",
sg_virt(areq_ctx->buff_sg),
- sg_dma_address(areq_ctx->buff_sg),
+ &sg_dma_address(areq_ctx->buff_sg),
sg_dma_len(areq_ctx->buff_sg));
dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
if (!do_revert) {
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index 712b21d..8d65e97 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -212,7 +212,7 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm)
}
SSI_LOG_DEBUG("Mapped key %u B at va=%pK to dma=%pad\n",
max_key_buf_size, ctx_p->user.key,
- ctx_p->user.key_dma_addr);
+ &ctx_p->user.key_dma_addr);
if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
/* Alloc hash tfm for essiv */
@@ -245,7 +245,7 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size,
DMA_TO_DEVICE);
SSI_LOG_DEBUG("Unmapped key buffer key_dma_addr=%pad\n",
- ctx_p->user.key_dma_addr);
+ &ctx_p->user.key_dma_addr);
/* Free key buffer in context */
kfree(ctx_p->user.key);
@@ -621,9 +621,9 @@ ssi_blkcipher_create_data_desc(
/* Process */
if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)) {
SSI_LOG_DEBUG(" data params addr %pad length 0x%X\n",
- sg_dma_address(src), nbytes);
+ &sg_dma_address(src), nbytes);
SSI_LOG_DEBUG(" data params addr %pad length 0x%X\n",
- sg_dma_address(dst), nbytes);
+ &sg_dma_address(dst), nbytes);
hw_desc_init(&desc[*seq_size]);
set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),
nbytes, NS_BIT);
@@ -637,7 +637,7 @@ ssi_blkcipher_create_data_desc(
} else {
/* bypass */
SSI_LOG_DEBUG(" bypass params addr %pad length 0x%X addr 0x%08X\n",
- req_ctx->mlli_params.mlli_dma_addr,
+ &req_ctx->mlli_params.mlli_dma_addr,
req_ctx->mlli_params.mlli_len,
(unsigned int)ctx_p->drvdata->mlli_sram_addr);
hw_desc_init(&desc[*seq_size]);
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 928c988..81cb63d 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -244,6 +244,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
/* Get device resources */
/* First CC registers space */
req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
+
/* Map registers space */
new_drvdata->cc_base = devm_ioremap_resource(&plat_dev->dev,
req_mem_cc_regs);
@@ -253,12 +254,9 @@ static int init_cc_resources(struct platform_device *plat_dev)
goto post_drvdata_err;
}
- SSI_LOG_DEBUG("Got MEM resource (%s): start=%pad end=%pad\n",
- req_mem_cc_regs->name,
- req_mem_cc_regs->start,
- req_mem_cc_regs->end);
- SSI_LOG_DEBUG("CC registers mapped from %pa to 0x%p\n",
- &req_mem_cc_regs->start, new_drvdata->cc_base);
+ SSI_LOG_DEBUG("Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
+ req_mem_cc_regs);
+ SSI_LOG_DEBUG("CC registers mapped to 0x%p\n", new_drvdata->cc_base);
cc_base = new_drvdata->cc_base;
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index 9b6476d..47c648a 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -100,7 +100,7 @@
#ifdef CC_DEBUG
#define SSI_LOG_DEBUG(format, ...) SSI_LOG(KERN_DEBUG, format, ##__VA_ARGS__)
#else /* Debug log messages are removed at compile time for non-DEBUG config. */
-#define SSI_LOG_DEBUG(format, ...) do {} while (0)
+#define SSI_LOG_DEBUG(format, ...) no_printk(format, ##__VA_ARGS__)
#endif
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 3e7873c..b7d6586 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -1,4 +1,4 @@
-/*
+ /*
* Copyright (C) 2012-2017 ARM Limited or its affiliates.
*
* This program is free software; you can redistribute it and/or modify
@@ -140,7 +140,7 @@ static int ssi_hash_map_result(struct device *dev,
}
SSI_LOG_DEBUG("Mapped digest result buffer %u B at va=%pK to dma=%pad\n",
digestsize, state->digest_result_buff,
- state->digest_result_dma_addr);
+ &state->digest_result_dma_addr);
return 0;
}
@@ -204,7 +204,7 @@ static int ssi_hash_map_request(struct device *dev,
}
SSI_LOG_DEBUG("Mapped digest %d B at va=%pK to dma=%pad\n",
ctx->inter_digestsize, state->digest_buff,
- state->digest_buff_dma_addr);
+ &state->digest_buff_dma_addr);
if (is_hmac) {
dma_sync_single_for_cpu(dev, ctx->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL);
@@ -253,7 +253,7 @@ static int ssi_hash_map_request(struct device *dev,
}
SSI_LOG_DEBUG("Mapped digest len %u B at va=%pK to dma=%pad\n",
HASH_LEN_SIZE, state->digest_bytes_len,
- state->digest_bytes_len_dma_addr);
+ &state->digest_bytes_len_dma_addr);
} else {
state->digest_bytes_len_dma_addr = 0;
}
@@ -268,7 +268,7 @@ static int ssi_hash_map_request(struct device *dev,
}
SSI_LOG_DEBUG("Mapped opad digest %d B at va=%pK to dma=%pad\n",
ctx->inter_digestsize, state->opad_digest_buff,
- state->opad_digest_dma_addr);
+ &state->opad_digest_dma_addr);
} else {
state->opad_digest_dma_addr = 0;
}
@@ -316,21 +316,21 @@ static void ssi_hash_unmap_request(struct device *dev,
dma_unmap_single(dev, state->digest_buff_dma_addr,
ctx->inter_digestsize, DMA_BIDIRECTIONAL);
SSI_LOG_DEBUG("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n",
- state->digest_buff_dma_addr);
+ &state->digest_buff_dma_addr);
state->digest_buff_dma_addr = 0;
}
if (state->digest_bytes_len_dma_addr != 0) {
dma_unmap_single(dev, state->digest_bytes_len_dma_addr,
HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
SSI_LOG_DEBUG("Unmapped digest-bytes-len buffer: digest_bytes_len_dma_addr=%pad\n",
- state->digest_bytes_len_dma_addr);
+ &state->digest_bytes_len_dma_addr);
state->digest_bytes_len_dma_addr = 0;
}
if (state->opad_digest_dma_addr != 0) {
dma_unmap_single(dev, state->opad_digest_dma_addr,
ctx->inter_digestsize, DMA_BIDIRECTIONAL);
SSI_LOG_DEBUG("Unmapped opad-digest: opad_digest_dma_addr=%pad\n",
- state->opad_digest_dma_addr);
+ &state->opad_digest_dma_addr);
state->opad_digest_dma_addr = 0;
}
@@ -353,7 +353,7 @@ static void ssi_hash_unmap_result(struct device *dev,
DMA_BIDIRECTIONAL);
SSI_LOG_DEBUG("unmpa digest result buffer va (%pK) pa (%pad) len %u\n",
state->digest_result_buff,
- state->digest_result_dma_addr,
+ &state->digest_result_dma_addr,
digestsize);
memcpy(result,
state->digest_result_buff,
@@ -997,7 +997,7 @@ static int ssi_hash_setkey(void *hash,
return -ENOMEM;
}
SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
- ctx->key_params.key_dma_addr,
+ &ctx->key_params.key_dma_addr,
ctx->key_params.keylen);
if (keylen > blocksize) {
@@ -1141,7 +1141,7 @@ static int ssi_hash_setkey(void *hash,
ctx->key_params.key_dma_addr,
ctx->key_params.keylen, DMA_TO_DEVICE);
SSI_LOG_DEBUG("Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n",
- ctx->key_params.key_dma_addr,
+ &ctx->key_params.key_dma_addr,
ctx->key_params.keylen);
}
return rc;
@@ -1179,7 +1179,7 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
return -ENOMEM;
}
SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
- ctx->key_params.key_dma_addr,
+ &ctx->key_params.key_dma_addr,
ctx->key_params.keylen);
ctx->is_hmac = true;
@@ -1227,7 +1227,7 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
ctx->key_params.key_dma_addr,
ctx->key_params.keylen, DMA_TO_DEVICE);
SSI_LOG_DEBUG("Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n",
- ctx->key_params.key_dma_addr,
+ &ctx->key_params.key_dma_addr,
ctx->key_params.keylen);
return rc;
@@ -1282,7 +1282,7 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx)
dma_unmap_single(dev, ctx->digest_buff_dma_addr,
sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL);
SSI_LOG_DEBUG("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n",
- ctx->digest_buff_dma_addr);
+ &ctx->digest_buff_dma_addr);
ctx->digest_buff_dma_addr = 0;
}
if (ctx->opad_tmp_keys_dma_addr != 0) {
@@ -1290,7 +1290,7 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx)
sizeof(ctx->opad_tmp_keys_buff),
DMA_BIDIRECTIONAL);
SSI_LOG_DEBUG("Unmapped opad-digest: opad_tmp_keys_dma_addr=%pad\n",
- ctx->opad_tmp_keys_dma_addr);
+ &ctx->opad_tmp_keys_dma_addr);
ctx->opad_tmp_keys_dma_addr = 0;
}
@@ -1311,7 +1311,7 @@ static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx)
}
SSI_LOG_DEBUG("Mapped digest %zu B at va=%pK to dma=%pad\n",
sizeof(ctx->digest_buff), ctx->digest_buff,
- ctx->digest_buff_dma_addr);
+ &ctx->digest_buff_dma_addr);
ctx->opad_tmp_keys_dma_addr = dma_map_single(dev, (void *)ctx->opad_tmp_keys_buff, sizeof(ctx->opad_tmp_keys_buff), DMA_BIDIRECTIONAL);
if (dma_mapping_error(dev, ctx->opad_tmp_keys_dma_addr)) {
@@ -1322,7 +1322,7 @@ static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx)
}
SSI_LOG_DEBUG("Mapped opad_tmp_keys %zu B at va=%pK to dma=%pad\n",
sizeof(ctx->opad_tmp_keys_buff), ctx->opad_tmp_keys_buff,
- ctx->opad_tmp_keys_dma_addr);
+ &ctx->opad_tmp_keys_dma_addr);
ctx->is_hmac = false;
return 0;
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index cae9904..27324bb 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -323,9 +323,9 @@ int send_request(
if (ssi_req->ivgen_dma_addr_len > 0) {
SSI_LOG_DEBUG("Acquire IV from pool into %d DMA addresses %pad, %pad, %pad, IV-size=%u\n",
ssi_req->ivgen_dma_addr_len,
- ssi_req->ivgen_dma_addr[0],
- ssi_req->ivgen_dma_addr[1],
- ssi_req->ivgen_dma_addr[2],
+ &ssi_req->ivgen_dma_addr[0],
+ &ssi_req->ivgen_dma_addr[1],
+ &ssi_req->ivgen_dma_addr[2],
ssi_req->ivgen_size);
/* Acquire IV from pool */
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 10/22] staging: ccree: rewrite GET_DMA_BUFFER_TYPE as func
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (8 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 09/22] staging: ccree: Fix format/argument mismatches Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 11/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
` (12 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
The GET_DMA_BUFFER_TYPE macro was triggering a macro argument reuse
warning from checkpatch. Rewrite the macro as inline function instead
to avoid risk of unintended side effects.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_buffer_mgr.c | 26 +++++++++++++++++---------
drivers/staging/ccree/ssi_buffer_mgr.h | 6 ++++--
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c
index 0b81fd5..4be7b51 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -34,11 +34,6 @@
#include "ssi_hash.h"
#include "ssi_aead.h"
-#define GET_DMA_BUFFER_TYPE(buff_type) ( \
- ((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \
- ((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \
- ((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID")
-
enum dma_buffer_type {
DMA_NULL_TYPE = -1,
DMA_SGL_TYPE = 1,
@@ -65,6 +60,19 @@ struct buffer_array {
u32 *mlli_nents[MAX_NUM_OF_BUFFERS_IN_MLLI];
};
+static const char *dma_buf_types[SSI_DMA_BUF_TYPE_MAX] = {
+ "BUF_NULL",
+ "BUF_DLLI",
+ "BUF_MLLI"
+ "BUF_INVALID"
+};
+
+static inline const char *dma_buf_type_str(enum ssi_req_dma_buf_type type)
+{
+ type = (type < SSI_DMA_BUF_INVL) ? type : SSI_DMA_BUF_INVL;
+ return dma_buf_types[type];
+}
+
/**
* ssi_buffer_mgr_get_sgl_nents() - Get scatterlist number of entries.
*
@@ -597,7 +605,7 @@ int ssi_buffer_mgr_map_blkcipher_request(
}
SSI_LOG_DEBUG("areq_ctx->dma_buf_type = %s\n",
- GET_DMA_BUFFER_TYPE(req_ctx->dma_buf_type));
+ dma_buf_type_str(req_ctx->dma_buf_type));
return 0;
@@ -827,7 +835,7 @@ static inline int ssi_buffer_mgr_aead_chain_assoc(
areq_ctx->assoc.nents = 0;
areq_ctx->assoc.mlli_nents = 0;
SSI_LOG_DEBUG("Chain assoc of length 0: buff_type=%s nents=%u\n",
- GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type),
+ dma_buf_type_str(areq_ctx->assoc_buff_type),
areq_ctx->assoc.nents);
goto chain_assoc_exit;
}
@@ -879,7 +887,7 @@ static inline int ssi_buffer_mgr_aead_chain_assoc(
if (unlikely((do_chain) ||
(areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI))) {
SSI_LOG_DEBUG("Chain assoc: buff_type=%s nents=%u\n",
- GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type),
+ dma_buf_type_str(areq_ctx->assoc_buff_type),
areq_ctx->assoc.nents);
ssi_buffer_mgr_add_scatterlist_entry(
sg_data, areq_ctx->assoc.nents,
@@ -1555,7 +1563,7 @@ int ssi_buffer_mgr_map_hash_request_final(
/* change the buffer index for the unmap function */
areq_ctx->buff_index = (areq_ctx->buff_index ^ 1);
SSI_LOG_DEBUG("areq_ctx->data_dma_buf_type = %s\n",
- GET_DMA_BUFFER_TYPE(areq_ctx->data_dma_buf_type));
+ dma_buf_type_str(areq_ctx->data_dma_buf_type));
return 0;
fail_unmap_din:
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.h b/drivers/staging/ccree/ssi_buffer_mgr.h
index 41f5223..93972fd 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.h
+++ b/drivers/staging/ccree/ssi_buffer_mgr.h
@@ -28,8 +28,10 @@
enum ssi_req_dma_buf_type {
SSI_DMA_BUF_NULL = 0,
- SSI_DMA_BUF_DLLI,
- SSI_DMA_BUF_MLLI
+ SSI_DMA_BUF_DLLI = 1,
+ SSI_DMA_BUF_MLLI = 2,
+ SSI_DMA_BUF_INVL = 3,
+ SSI_DMA_BUF_TYPE_MAX = 4
};
enum ssi_sg_cpy_direct {
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 11/22] staging: ccree: fix line indentation and breaks
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (9 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 10/22] staging: ccree: rewrite GET_DMA_BUFFER_TYPE as func Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:44 ` Joe Perches
2017-08-16 22:08 ` Greg Kroah-Hartman
2017-08-15 6:26 ` [PATCH v3 12/22] staging: ccree: align box comment correctly Gilad Ben-Yossef
` (11 subsequent siblings)
22 siblings, 2 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Fix wrong indentation and line breaks, including missing tabs,
breaking lines longer then 80 char or wrongly broken.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_driver.c | 107 +++++++++++++++++++++++--------------
1 file changed, 67 insertions(+), 40 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 81cb63d..0ce2f57 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -87,27 +87,31 @@ void dump_byte_array(const char *name, const u8 *the_array, unsigned long size)
ret = snprintf(line_buf, sizeof(line_buf), "%s[%lu]: ", name, size);
if (ret < 0) {
- SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret);
+ SSI_LOG_ERR
+ ("snprintf returned %d . aborting buffer array dump\n",
+ ret);
return;
}
line_offset = ret;
for (i = 0, cur_byte = the_array;
(i < size) && (line_offset < sizeof(line_buf)); i++, cur_byte++) {
- ret = snprintf(line_buf + line_offset,
- sizeof(line_buf) - line_offset,
- "0x%02X ", *cur_byte);
+ ret = snprintf(line_buf + line_offset,
+ sizeof(line_buf) - line_offset,
+ "0x%02X ", *cur_byte);
if (ret < 0) {
- SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret);
+ SSI_LOG_ERR
+ ("snprintf returned %d . aborting buffer array dump\n",
+ ret);
return;
}
line_offset += ret;
- if (line_offset > 75) { /* Cut before line end */
+ if (line_offset > 75) { /* Cut before line end */
SSI_LOG_DEBUG("%s\n", line_buf);
line_offset = 0;
}
}
- if (line_offset > 0) /* Dump remaining line */
+ if (line_offset > 0) /* Dump remaining line */
SSI_LOG_DEBUG("%s\n", line_buf);
}
#endif
@@ -124,7 +128,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
/* read the interrupt status */
irr = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRR));
SSI_LOG_DEBUG("Got IRR=0x%08X\n", irr);
- if (unlikely(irr == 0)) { /* Probably shared interrupt line */
+ if (unlikely(irr == 0)) { /* Probably shared interrupt line */
SSI_LOG_ERR("Got interrupt with empty IRR\n");
return IRQ_NONE;
}
@@ -137,7 +141,8 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
/* Completion interrupt - most probable */
if (likely((irr & SSI_COMP_IRQ_MASK) != 0)) {
/* Mask AXI completion interrupt - will be unmasked in Deferred service handler */
- CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), imr | SSI_COMP_IRQ_MASK);
+ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR),
+ imr | SSI_COMP_IRQ_MASK);
irr &= ~SSI_COMP_IRQ_MASK;
complete_request(drvdata);
}
@@ -145,7 +150,8 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
/* TEE FIPS interrupt */
if (likely((irr & SSI_GPR0_IRQ_MASK) != 0)) {
/* Mask interrupt - will be unmasked in Deferred service handler */
- CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), imr | SSI_GPR0_IRQ_MASK);
+ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR),
+ imr | SSI_GPR0_IRQ_MASK);
irr &= ~SSI_GPR0_IRQ_MASK;
fips_handler(drvdata);
}
@@ -155,14 +161,18 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
u32 axi_err;
/* Read the AXI error ID */
- axi_err = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR));
- SSI_LOG_DEBUG("AXI completion error: axim_mon_err=0x%08X\n", axi_err);
+ axi_err =
+ CC_HAL_READ_REGISTER(CC_REG_OFFSET
+ (CRY_KERNEL, AXIM_MON_ERR));
+ SSI_LOG_DEBUG("AXI completion error: axim_mon_err=0x%08X\n",
+ axi_err);
irr &= ~SSI_AXI_ERR_IRQ_MASK;
}
if (unlikely(irr != 0)) {
- SSI_LOG_DEBUG("IRR includes unknown cause bits (0x%08X)\n", irr);
+ SSI_LOG_DEBUG("IRR includes unknown cause bits (0x%08X)\n",
+ irr);
/* Just warning */
}
@@ -176,8 +186,11 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
/* Unmask all AXI interrupt sources AXI_CFG1 register */
val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CFG));
- CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CFG), val & ~SSI_AXI_IRQ_MASK);
- SSI_LOG_DEBUG("AXIM_CFG=0x%08X\n", CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CFG)));
+ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CFG),
+ val & ~SSI_AXI_IRQ_MASK);
+ SSI_LOG_DEBUG("AXIM_CFG=0x%08X\n",
+ CC_HAL_READ_REGISTER(CC_REG_OFFSET
+ (CRY_KERNEL, AXIM_CFG)));
/* Clear all pending interrupts */
val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRR));
@@ -194,22 +207,27 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRQ_TIMER_INIT_VAL),
DX_IRQ_DELAY);
#endif
- if (CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRQ_TIMER_INIT_VAL)) > 0) {
+ if (CC_HAL_READ_REGISTER
+ (CC_REG_OFFSET(HOST_RGF, HOST_IRQ_TIMER_INIT_VAL)) > 0) {
SSI_LOG_DEBUG("irq_delay=%d CC cycles\n",
- CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRQ_TIMER_INIT_VAL)));
+ CC_HAL_READ_REGISTER(CC_REG_OFFSET
+ (HOST_RGF,
+ HOST_IRQ_TIMER_INIT_VAL)));
}
#endif
cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);
- val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS));
+ val =
+ CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS));
if (is_probe)
SSI_LOG_INFO("Cache params previous: 0x%08X\n", val);
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS),
cache_params);
- val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS));
+ val =
+ CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS));
if (is_probe)
SSI_LOG_INFO("Cache params current: 0x%08X (expect: 0x%08X)\n",
@@ -282,31 +300,37 @@ static int init_cc_resources(struct platform_device *plat_dev)
goto post_drvdata_err;
if (!new_drvdata->plat_dev->dev.dma_mask)
- new_drvdata->plat_dev->dev.dma_mask = &new_drvdata->plat_dev->dev.coherent_dma_mask;
+ new_drvdata->plat_dev->dev.dma_mask =
+ &new_drvdata->plat_dev->dev.coherent_dma_mask;
if (!new_drvdata->plat_dev->dev.coherent_dma_mask)
- new_drvdata->plat_dev->dev.coherent_dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN);
+ new_drvdata->plat_dev->dev.coherent_dma_mask =
+ DMA_BIT_MASK(DMA_BIT_MASK_LEN);
/* Verify correct mapping */
- signature_val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_SIGNATURE));
+ signature_val =
+ CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_SIGNATURE));
if (signature_val != DX_DEV_SIGNATURE) {
- SSI_LOG_ERR("Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
- signature_val, (u32)DX_DEV_SIGNATURE);
+ SSI_LOG_ERR
+ ("Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
+ signature_val, (u32)DX_DEV_SIGNATURE);
rc = -EINVAL;
goto post_clk_err;
}
SSI_LOG_DEBUG("CC SIGNATURE=0x%08X\n", signature_val);
/* Display HW versions */
- SSI_LOG(KERN_INFO, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n", SSI_DEV_NAME_STR,
- CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_VERSION)), DRV_MODULE_VERSION);
+ SSI_LOG(KERN_INFO,
+ "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
+ SSI_DEV_NAME_STR,
+ CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_VERSION)),
+ DRV_MODULE_VERSION);
rc = init_cc_regs(new_drvdata, true);
if (unlikely(rc != 0)) {
SSI_LOG_ERR("init_cc_regs failed\n");
goto post_clk_err;
}
-
#ifdef ENABLE_CC_SYSFS
rc = ssi_sysfs_init(&plat_dev->dev.kobj, new_drvdata);
if (unlikely(rc != 0)) {
@@ -327,7 +351,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
}
new_drvdata->mlli_sram_addr =
- ssi_sram_mgr_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
+ ssi_sram_mgr_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
if (unlikely(new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR)) {
SSI_LOG_ERR("Failed to alloc MLLI Sram buffer\n");
rc = -ENOMEM;
@@ -395,7 +419,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
post_power_mgr_err:
ssi_power_mgr_fini(new_drvdata);
post_buf_mgr_err:
- ssi_buffer_mgr_fini(new_drvdata);
+ ssi_buffer_mgr_fini(new_drvdata);
post_req_mgr_err:
request_mgr_fini(new_drvdata);
post_sram_mgr_err:
@@ -426,7 +450,7 @@ void fini_cc_regs(struct ssi_drvdata *drvdata)
static void cleanup_cc_resources(struct platform_device *plat_dev)
{
struct ssi_drvdata *drvdata =
- (struct ssi_drvdata *)dev_get_drvdata(&plat_dev->dev);
+ (struct ssi_drvdata *)dev_get_drvdata(&plat_dev->dev);
ssi_aead_free(drvdata);
ssi_hash_free(drvdata);
@@ -478,15 +502,17 @@ static int cc7x_probe(struct platform_device *plat_dev)
#if defined(CONFIG_ARM) && defined(CC_DEBUG)
u32 ctr, cacheline_size;
- asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
- cacheline_size = 4 << ((ctr >> 16) & 0xf);
- SSI_LOG_DEBUG("CP15(L1_CACHE_BYTES) = %u , Kconfig(L1_CACHE_BYTES) = %u\n",
- cacheline_size, L1_CACHE_BYTES);
-
- asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (ctr));
- SSI_LOG_DEBUG("Main ID register (MIDR): Implementer 0x%02X, Arch 0x%01X, Part 0x%03X, Rev r%dp%d\n",
- (ctr >> 24), (ctr >> 16) & 0xF, (ctr >> 4) & 0xFFF,
- (ctr >> 20) & 0xF, ctr & 0xF);
+ asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+ cacheline_size = 4 << ((ctr >> 16) & 0xf);
+ SSI_LOG_DEBUG
+ ("CP15(L1_CACHE_BYTES) = %u , Kconfig(L1_CACHE_BYTES) = %u\n",
+ cacheline_size, L1_CACHE_BYTES);
+
+ asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (ctr));
+ SSI_LOG_DEBUG
+ ("Main ID register (MIDR): Implementer 0x%02X, Arch 0x%01X, Part 0x%03X, Rev r%dp%d\n",
+ (ctr >> 24), (ctr >> 16) & 0xF, (ctr >> 4) & 0xFFF,
+ (ctr >> 20) & 0xF, ctr & 0xF);
#endif
/* Map registers space */
@@ -512,7 +538,8 @@ static int cc7x_remove(struct platform_device *plat_dev)
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
static struct dev_pm_ops arm_cc7x_driver_pm = {
- SET_RUNTIME_PM_OPS(ssi_power_mgr_runtime_suspend, ssi_power_mgr_runtime_resume, NULL)
+ SET_RUNTIME_PM_OPS(ssi_power_mgr_runtime_suspend,
+ ssi_power_mgr_runtime_resume, NULL)
};
#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v3 11/22] staging: ccree: fix line indentation and breaks
2017-08-15 6:26 ` [PATCH v3 11/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
@ 2017-08-15 6:44 ` Joe Perches
2017-08-16 22:08 ` Greg Kroah-Hartman
1 sibling, 0 replies; 26+ messages in thread
From: Joe Perches @ 2017-08-15 6:44 UTC (permalink / raw)
To: Gilad Ben-Yossef, Greg Kroah-Hartman, linux-crypto,
driverdev-devel, devel, linux-kernel
Cc: Ofir Drang
On Tue, 2017-08-15 at 09:26 +0300, Gilad Ben-Yossef wrote:
> Fix wrong indentation and line breaks, including missing tabs,
> breaking lines longer then 80 char or wrongly broken.
[]
> diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
[]
> - SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret);
> + SSI_LOG_ERR
> + ("snprintf returned %d . aborting buffer array dump\n",
> + ret);
This change is quite unpleasant to read.
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v3 11/22] staging: ccree: fix line indentation and breaks
2017-08-15 6:26 ` [PATCH v3 11/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
2017-08-15 6:44 ` Joe Perches
@ 2017-08-16 22:08 ` Greg Kroah-Hartman
1 sibling, 0 replies; 26+ messages in thread
From: Greg Kroah-Hartman @ 2017-08-16 22:08 UTC (permalink / raw)
To: Gilad Ben-Yossef
Cc: linux-crypto, driverdev-devel, devel, linux-kernel, Ofir Drang
On Tue, Aug 15, 2017 at 09:26:39AM +0300, Gilad Ben-Yossef wrote:
> Fix wrong indentation and line breaks, including missing tabs,
> breaking lines longer then 80 char or wrongly broken.
>
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
> ---
> drivers/staging/ccree/ssi_driver.c | 107 +++++++++++++++++++++++--------------
> 1 file changed, 67 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
> index 81cb63d..0ce2f57 100644
> --- a/drivers/staging/ccree/ssi_driver.c
> +++ b/drivers/staging/ccree/ssi_driver.c
> @@ -87,27 +87,31 @@ void dump_byte_array(const char *name, const u8 *the_array, unsigned long size)
>
> ret = snprintf(line_buf, sizeof(line_buf), "%s[%lu]: ", name, size);
> if (ret < 0) {
> - SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret);
> + SSI_LOG_ERR
> + ("snprintf returned %d . aborting buffer array dump\n",
> + ret);
As Joe said, this is pretty bad. Just move "ret);" to the next line,
and then fix it up so that there are not SSI_LOG_ERR() macros and use
the normal in-kernel printing functions instead, then you will not get
this type of warning.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 12/22] staging: ccree: align box comment correctly
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (10 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 11/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 13/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
` (10 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Fix indentation in first comment.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_hash.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index b7d6586..b95c3ce 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -1,18 +1,18 @@
/*
- * Copyright (C) 2012-2017 ARM Limited or its affiliates.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- */
+ * Copyright (C) 2012-2017 ARM Limited or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
#include <linux/kernel.h>
#include <linux/module.h>
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 13/22] staging: ccree: fix line indentation and breaks
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (11 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 12/22] staging: ccree: align box comment correctly Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 14/22] staging: ccree: fix struct init braces Gilad Ben-Yossef
` (9 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Fix source line indentation and breaks
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_hash.c | 494 ++++++++++++++++++++++-----------------
1 file changed, 284 insertions(+), 210 deletions(-)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index b95c3ce..e2dc5d8 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -33,7 +33,6 @@
#define SSI_MAX_AHASH_SEQ_LEN 12
#define SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE MAX(SSI_MAX_HASH_BLCK_SIZE, 3 * AES_BLOCK_SIZE)
-
struct ssi_hash_handle {
ssi_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/
ssi_sram_addr_t larval_digest_sram_addr; /* const value in SRAM */
@@ -64,10 +63,9 @@ static const u64 sha512_init[] = {
SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 };
#endif
-static void ssi_hash_create_xcbc_setup(
- struct ahash_request *areq,
- struct cc_hw_desc desc[],
- unsigned int *seq_size);
+static void ssi_hash_create_xcbc_setup(struct ahash_request *areq,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size);
static void ssi_hash_create_cmac_setup(struct ahash_request *areq,
struct cc_hw_desc desc[],
@@ -94,7 +92,8 @@ struct ssi_hash_ctx {
* the initial digest if HASH.
*/
u8 digest_buff[SSI_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
- u8 opad_tmp_keys_buff[SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE] ____cacheline_aligned;
+ u8 opad_tmp_keys_buff[SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE]
+ ____cacheline_aligned;
dma_addr_t opad_tmp_keys_dma_addr ____cacheline_aligned;
dma_addr_t digest_buff_dma_addr;
@@ -107,18 +106,17 @@ struct ssi_hash_ctx {
bool is_hmac;
};
-static void ssi_hash_create_data_desc(
- struct ahash_req_ctx *areq_ctx,
- struct ssi_hash_ctx *ctx,
- unsigned int flow_mode, struct cc_hw_desc desc[],
- bool is_not_last_data,
- unsigned int *seq_size);
+static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx,
+ struct ssi_hash_ctx *ctx,
+ unsigned int flow_mode,
+ struct cc_hw_desc desc[],
+ bool is_not_last_data,
+ unsigned int *seq_size);
static inline void ssi_set_hash_endianity(u32 mode, struct cc_hw_desc *desc)
{
if (unlikely((mode == DRV_HASH_MD5) ||
- (mode == DRV_HASH_SHA384) ||
- (mode == DRV_HASH_SHA512))) {
+ (mode == DRV_HASH_SHA384) || (mode == DRV_HASH_SHA512))) {
set_bytes_swap(desc, 1);
} else {
set_cipher_config0(desc, HASH_DIGEST_RESULT_LITTLE_ENDIAN);
@@ -130,17 +128,18 @@ static int ssi_hash_map_result(struct device *dev,
unsigned int digestsize)
{
state->digest_result_dma_addr =
- dma_map_single(dev, (void *)state->digest_result_buff,
- digestsize,
- DMA_BIDIRECTIONAL);
+ dma_map_single(dev, (void *)state->digest_result_buff,
+ digestsize, DMA_BIDIRECTIONAL);
if (unlikely(dma_mapping_error(dev, state->digest_result_dma_addr))) {
- SSI_LOG_ERR("Mapping digest result buffer %u B for DMA failed\n",
- digestsize);
+ SSI_LOG_ERR
+ ("Mapping digest result buffer %u B for DMA failed\n",
+ digestsize);
return -ENOMEM;
}
- SSI_LOG_DEBUG("Mapped digest result buffer %u B at va=%pK to dma=%pad\n",
- digestsize, state->digest_result_buff,
- &state->digest_result_dma_addr);
+ SSI_LOG_DEBUG
+ ("Mapped digest result buffer %u B at va=%pK to dma=%pad\n",
+ digestsize, state->digest_result_buff,
+ &state->digest_result_dma_addr);
return 0;
}
@@ -150,8 +149,8 @@ static int ssi_hash_map_request(struct device *dev,
struct ssi_hash_ctx *ctx)
{
bool is_hmac = ctx->is_hmac;
- ssi_sram_addr_t larval_digest_addr = ssi_ahash_get_larval_digest_sram_addr(
- ctx->drvdata, ctx->hash_mode);
+ ssi_sram_addr_t larval_digest_addr =
+ ssi_ahash_get_larval_digest_sram_addr(ctx->drvdata, ctx->hash_mode);
struct ssi_crypto_req ssi_req = {};
struct cc_hw_desc desc;
int rc = -ENOMEM;
@@ -166,40 +165,56 @@ static int ssi_hash_map_request(struct device *dev,
SSI_LOG_ERR("Allocating buff1 in context failed\n");
goto fail_buff0;
}
- state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE, GFP_KERNEL | GFP_DMA);
+ state->digest_result_buff =
+ kzalloc(SSI_MAX_HASH_DIGEST_SIZE, GFP_KERNEL | GFP_DMA);
if (!state->digest_result_buff) {
- SSI_LOG_ERR("Allocating digest_result_buff in context failed\n");
+ SSI_LOG_ERR
+ ("Allocating digest_result_buff in context failed\n");
goto fail_buff1;
}
- state->digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA);
+ state->digest_buff =
+ kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA);
if (!state->digest_buff) {
SSI_LOG_ERR("Allocating digest-buffer in context failed\n");
goto fail_digest_result_buff;
}
- SSI_LOG_DEBUG("Allocated digest-buffer in context ctx->digest_buff=@%p\n", state->digest_buff);
+ SSI_LOG_DEBUG
+ ("Allocated digest-buffer in context ctx->digest_buff=@%p\n",
+ state->digest_buff);
if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) {
- state->digest_bytes_len = kzalloc(HASH_LEN_SIZE, GFP_KERNEL | GFP_DMA);
+ state->digest_bytes_len =
+ kzalloc(HASH_LEN_SIZE, GFP_KERNEL | GFP_DMA);
if (!state->digest_bytes_len) {
- SSI_LOG_ERR("Allocating digest-bytes-len in context failed\n");
+ SSI_LOG_ERR
+ ("Allocating digest-bytes-len in context failed\n");
goto fail1;
}
- SSI_LOG_DEBUG("Allocated digest-bytes-len in context state->>digest_bytes_len=@%p\n", state->digest_bytes_len);
+ SSI_LOG_DEBUG
+ ("Allocated digest-bytes-len in context state->>digest_bytes_len=@%p\n",
+ state->digest_bytes_len);
} else {
state->digest_bytes_len = NULL;
}
- state->opad_digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA);
+ state->opad_digest_buff =
+ kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA);
if (!state->opad_digest_buff) {
- SSI_LOG_ERR("Allocating opad-digest-buffer in context failed\n");
+ SSI_LOG_ERR
+ ("Allocating opad-digest-buffer in context failed\n");
goto fail2;
}
- SSI_LOG_DEBUG("Allocated opad-digest-buffer in context state->digest_bytes_len=@%p\n", state->opad_digest_buff);
+ SSI_LOG_DEBUG
+ ("Allocated opad-digest-buffer in context state->digest_bytes_len=@%p\n",
+ state->opad_digest_buff);
- state->digest_buff_dma_addr = dma_map_single(dev, (void *)state->digest_buff, ctx->inter_digestsize, DMA_BIDIRECTIONAL);
+ state->digest_buff_dma_addr =
+ dma_map_single(dev, (void *)state->digest_buff,
+ ctx->inter_digestsize, DMA_BIDIRECTIONAL);
if (dma_mapping_error(dev, state->digest_buff_dma_addr)) {
- SSI_LOG_ERR("Mapping digest len %d B at va=%pK for DMA failed\n",
- ctx->inter_digestsize, state->digest_buff);
+ SSI_LOG_ERR
+ ("Mapping digest len %d B at va=%pK for DMA failed\n",
+ ctx->inter_digestsize, state->digest_buff);
goto fail3;
}
SSI_LOG_DEBUG("Mapped digest %d B at va=%pK to dma=%pad\n",
@@ -207,27 +222,42 @@ static int ssi_hash_map_request(struct device *dev,
&state->digest_buff_dma_addr);
if (is_hmac) {
- dma_sync_single_for_cpu(dev, ctx->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL);
- if ((ctx->hw_mode == DRV_CIPHER_XCBC_MAC) || (ctx->hw_mode == DRV_CIPHER_CMAC)) {
+ dma_sync_single_for_cpu(dev, ctx->digest_buff_dma_addr,
+ ctx->inter_digestsize,
+ DMA_BIDIRECTIONAL);
+ if ((ctx->hw_mode == DRV_CIPHER_XCBC_MAC) ||
+ (ctx->hw_mode == DRV_CIPHER_CMAC)) {
memset(state->digest_buff, 0, ctx->inter_digestsize);
- } else { /*sha*/
- memcpy(state->digest_buff, ctx->digest_buff, ctx->inter_digestsize);
+ } else { /*sha */
+ memcpy(state->digest_buff, ctx->digest_buff,
+ ctx->inter_digestsize);
#if (DX_DEV_SHA_MAX > 256)
- if (unlikely((ctx->hash_mode == DRV_HASH_SHA512) || (ctx->hash_mode == DRV_HASH_SHA384)))
- memcpy(state->digest_bytes_len, digest_len_sha512_init, HASH_LEN_SIZE);
+ if (unlikely
+ ((ctx->hash_mode == DRV_HASH_SHA512) ||
+ (ctx->hash_mode == DRV_HASH_SHA384)))
+ memcpy(state->digest_bytes_len,
+ digest_len_sha512_init, HASH_LEN_SIZE);
else
- memcpy(state->digest_bytes_len, digest_len_init, HASH_LEN_SIZE);
+ memcpy(state->digest_bytes_len, digest_len_init,
+ HASH_LEN_SIZE);
#else
- memcpy(state->digest_bytes_len, digest_len_init, HASH_LEN_SIZE);
+ memcpy(state->digest_bytes_len, digest_len_init,
+ HASH_LEN_SIZE);
#endif
}
- dma_sync_single_for_device(dev, state->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL);
+ dma_sync_single_for_device(dev, state->digest_buff_dma_addr,
+ ctx->inter_digestsize,
+ DMA_BIDIRECTIONAL);
if (ctx->hash_mode != DRV_HASH_NULL) {
- dma_sync_single_for_cpu(dev, ctx->opad_tmp_keys_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL);
- memcpy(state->opad_digest_buff, ctx->opad_tmp_keys_buff, ctx->inter_digestsize);
+ dma_sync_single_for_cpu(dev,
+ ctx->opad_tmp_keys_dma_addr,
+ ctx->inter_digestsize,
+ DMA_BIDIRECTIONAL);
+ memcpy(state->opad_digest_buff, ctx->opad_tmp_keys_buff,
+ ctx->inter_digestsize);
}
- } else { /*hash*/
+ } else { /*hash */
/* Copy the initial digests if hash flow. The SRAM contains the
* initial digests in the expected order for all SHA*
*/
@@ -245,10 +275,13 @@ static int ssi_hash_map_request(struct device *dev,
}
if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) {
- state->digest_bytes_len_dma_addr = dma_map_single(dev, (void *)state->digest_bytes_len, HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
+ state->digest_bytes_len_dma_addr =
+ dma_map_single(dev, (void *)state->digest_bytes_len,
+ HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
if (dma_mapping_error(dev, state->digest_bytes_len_dma_addr)) {
- SSI_LOG_ERR("Mapping digest len %u B at va=%pK for DMA failed\n",
- HASH_LEN_SIZE, state->digest_bytes_len);
+ SSI_LOG_ERR
+ ("Mapping digest len %u B at va=%pK for DMA failed\n",
+ HASH_LEN_SIZE, state->digest_bytes_len);
goto fail4;
}
SSI_LOG_DEBUG("Mapped digest len %u B at va=%pK to dma=%pad\n",
@@ -259,11 +292,13 @@ static int ssi_hash_map_request(struct device *dev,
}
if (is_hmac && ctx->hash_mode != DRV_HASH_NULL) {
- state->opad_digest_dma_addr = dma_map_single(dev, (void *)state->opad_digest_buff, ctx->inter_digestsize, DMA_BIDIRECTIONAL);
+ state->opad_digest_dma_addr =
+ dma_map_single(dev, (void *)state->opad_digest_buff,
+ ctx->inter_digestsize, DMA_BIDIRECTIONAL);
if (dma_mapping_error(dev, state->opad_digest_dma_addr)) {
- SSI_LOG_ERR("Mapping opad digest %d B at va=%pK for DMA failed\n",
- ctx->inter_digestsize,
- state->opad_digest_buff);
+ SSI_LOG_ERR
+ ("Mapping opad digest %d B at va=%pK for DMA failed\n",
+ ctx->inter_digestsize, state->opad_digest_buff);
goto fail5;
}
SSI_LOG_DEBUG("Mapped opad digest %d B at va=%pK to dma=%pad\n",
@@ -281,12 +316,14 @@ static int ssi_hash_map_request(struct device *dev,
fail5:
if (state->digest_bytes_len_dma_addr != 0) {
- dma_unmap_single(dev, state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
+ dma_unmap_single(dev, state->digest_bytes_len_dma_addr,
+ HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
state->digest_bytes_len_dma_addr = 0;
}
fail4:
if (state->digest_buff_dma_addr != 0) {
- dma_unmap_single(dev, state->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL);
+ dma_unmap_single(dev, state->digest_buff_dma_addr,
+ ctx->inter_digestsize, DMA_BIDIRECTIONAL);
state->digest_buff_dma_addr = 0;
}
fail3:
@@ -294,7 +331,7 @@ static int ssi_hash_map_request(struct device *dev,
fail2:
kfree(state->digest_bytes_len);
fail1:
- kfree(state->digest_buff);
+ kfree(state->digest_buff);
fail_digest_result_buff:
kfree(state->digest_result_buff);
state->digest_result_buff = NULL;
@@ -315,22 +352,25 @@ static void ssi_hash_unmap_request(struct device *dev,
if (state->digest_buff_dma_addr != 0) {
dma_unmap_single(dev, state->digest_buff_dma_addr,
ctx->inter_digestsize, DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n",
- &state->digest_buff_dma_addr);
+ SSI_LOG_DEBUG
+ ("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n",
+ &state->digest_buff_dma_addr);
state->digest_buff_dma_addr = 0;
}
if (state->digest_bytes_len_dma_addr != 0) {
dma_unmap_single(dev, state->digest_bytes_len_dma_addr,
HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("Unmapped digest-bytes-len buffer: digest_bytes_len_dma_addr=%pad\n",
- &state->digest_bytes_len_dma_addr);
+ SSI_LOG_DEBUG
+ ("Unmapped digest-bytes-len buffer: digest_bytes_len_dma_addr=%pad\n",
+ &state->digest_bytes_len_dma_addr);
state->digest_bytes_len_dma_addr = 0;
}
if (state->opad_digest_dma_addr != 0) {
dma_unmap_single(dev, state->opad_digest_dma_addr,
ctx->inter_digestsize, DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("Unmapped opad-digest: opad_digest_dma_addr=%pad\n",
- &state->opad_digest_dma_addr);
+ SSI_LOG_DEBUG
+ ("Unmapped opad-digest: opad_digest_dma_addr=%pad\n",
+ &state->opad_digest_dma_addr);
state->opad_digest_dma_addr = 0;
}
@@ -349,20 +389,18 @@ static void ssi_hash_unmap_result(struct device *dev,
if (state->digest_result_dma_addr != 0) {
dma_unmap_single(dev,
state->digest_result_dma_addr,
- digestsize,
- DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("unmpa digest result buffer va (%pK) pa (%pad) len %u\n",
- state->digest_result_buff,
- &state->digest_result_dma_addr,
- digestsize);
- memcpy(result,
- state->digest_result_buff,
- digestsize);
+ digestsize, DMA_BIDIRECTIONAL);
+ SSI_LOG_DEBUG
+ ("unmpa digest result buffer va (%pK) pa (%pad) len %u\n",
+ state->digest_result_buff, &state->digest_result_dma_addr,
+ digestsize);
+ memcpy(result, state->digest_result_buff, digestsize);
}
state->digest_result_dma_addr = 0;
}
-static void ssi_hash_update_complete(struct device *dev, void *ssi_req, void __iomem *cc_base)
+static void ssi_hash_update_complete(struct device *dev, void *ssi_req,
+ void __iomem *cc_base)
{
struct ahash_request *req = (struct ahash_request *)ssi_req;
struct ahash_req_ctx *state = ahash_request_ctx(req);
@@ -373,7 +411,8 @@ static void ssi_hash_update_complete(struct device *dev, void *ssi_req, void __i
req->base.complete(&req->base, 0);
}
-static void ssi_hash_digest_complete(struct device *dev, void *ssi_req, void __iomem *cc_base)
+static void ssi_hash_digest_complete(struct device *dev, void *ssi_req,
+ void __iomem *cc_base)
{
struct ahash_request *req = (struct ahash_request *)ssi_req;
struct ahash_req_ctx *state = ahash_request_ctx(req);
@@ -389,7 +428,8 @@ static void ssi_hash_digest_complete(struct device *dev, void *ssi_req, void __i
req->base.complete(&req->base, 0);
}
-static void ssi_hash_complete(struct device *dev, void *ssi_req, void __iomem *cc_base)
+static void ssi_hash_complete(struct device *dev, void *ssi_req,
+ void __iomem *cc_base)
{
struct ahash_request *req = (struct ahash_request *)ssi_req;
struct ahash_req_ctx *state = ahash_request_ctx(req);
@@ -409,19 +449,19 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
struct ssi_hash_ctx *ctx,
unsigned int digestsize,
struct scatterlist *src,
- unsigned int nbytes, u8 *result,
- void *async_req)
+ unsigned int nbytes, u8 *result, void *async_req)
{
struct device *dev = &ctx->drvdata->plat_dev->dev;
bool is_hmac = ctx->is_hmac;
struct ssi_crypto_req ssi_req = {};
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
- ssi_sram_addr_t larval_digest_addr = ssi_ahash_get_larval_digest_sram_addr(
- ctx->drvdata, ctx->hash_mode);
+ ssi_sram_addr_t larval_digest_addr =
+ ssi_ahash_get_larval_digest_sram_addr(ctx->drvdata, ctx->hash_mode);
int idx = 0;
int rc = 0;
- SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
+ SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash",
+ nbytes);
if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) {
SSI_LOG_ERR("map_ahash_source() failed\n");
@@ -433,7 +473,9 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
return -ENOMEM;
}
- if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) {
+ if (unlikely
+ (ssi_buffer_mgr_map_hash_request_final
+ (ctx->drvdata, state, src, nbytes, 1) != 0)) {
SSI_LOG_ERR("map_ahash_request_final() failed\n");
return -ENOMEM;
}
@@ -513,8 +555,9 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
hw_desc_init(&desc[idx]);
set_cipher_mode(&desc[idx], ctx->hw_mode);
set_din_sram(&desc[idx],
- ssi_ahash_get_initial_digest_len_sram_addr(
-ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
+ ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata,
+ ctx->hash_mode),
+ HASH_LEN_SIZE);
set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
set_flow_mode(&desc[idx], S_DIN_to_HASH);
set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
@@ -552,7 +595,8 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1);
if (unlikely(rc != -EINPROGRESS)) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
ssi_hash_unmap_result(dev, state, digestsize, result);
ssi_hash_unmap_request(dev, state, ctx);
}
@@ -560,9 +604,11 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0);
if (rc != 0) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
} else {
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, false);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ false);
}
ssi_hash_unmap_result(dev, state, digestsize, result);
ssi_hash_unmap_request(dev, state, ctx);
@@ -574,8 +620,7 @@ static int ssi_hash_update(struct ahash_req_ctx *state,
struct ssi_hash_ctx *ctx,
unsigned int block_size,
struct scatterlist *src,
- unsigned int nbytes,
- void *async_req)
+ unsigned int nbytes, void *async_req)
{
struct device *dev = &ctx->drvdata->plat_dev->dev;
struct ssi_crypto_req ssi_req = {};
@@ -584,14 +629,15 @@ static int ssi_hash_update(struct ahash_req_ctx *state,
int rc;
SSI_LOG_DEBUG("===== %s-update (%d) ====\n", ctx->is_hmac ?
- "hmac" : "hash", nbytes);
+ "hmac" : "hash", nbytes);
if (nbytes == 0) {
/* no real updates required */
return 0;
}
- rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state, src, nbytes, block_size);
+ rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state, src,
+ nbytes, block_size);
if (unlikely(rc)) {
if (rc == 1) {
SSI_LOG_DEBUG(" data size not require HW update %x\n",
@@ -652,15 +698,18 @@ static int ssi_hash_update(struct ahash_req_ctx *state,
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1);
if (unlikely(rc != -EINPROGRESS)) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
}
} else {
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0);
if (rc != 0) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
} else {
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, false);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ false);
}
}
return rc;
@@ -670,9 +719,7 @@ static int ssi_hash_finup(struct ahash_req_ctx *state,
struct ssi_hash_ctx *ctx,
unsigned int digestsize,
struct scatterlist *src,
- unsigned int nbytes,
- u8 *result,
- void *async_req)
+ unsigned int nbytes, u8 *result, void *async_req)
{
struct device *dev = &ctx->drvdata->plat_dev->dev;
bool is_hmac = ctx->is_hmac;
@@ -681,9 +728,12 @@ static int ssi_hash_finup(struct ahash_req_ctx *state,
int idx = 0;
int rc;
- SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
+ SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac ? "hmac" : "hash",
+ nbytes);
- if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) {
+ if (unlikely
+ (ssi_buffer_mgr_map_hash_request_final
+ (ctx->drvdata, state, src, nbytes, 1) != 0)) {
SSI_LOG_ERR("map_ahash_request_final() failed\n");
return -ENOMEM;
}
@@ -743,8 +793,9 @@ static int ssi_hash_finup(struct ahash_req_ctx *state,
hw_desc_init(&desc[idx]);
set_cipher_mode(&desc[idx], ctx->hw_mode);
set_din_sram(&desc[idx],
- ssi_ahash_get_initial_digest_len_sram_addr(
-ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
+ ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata,
+ ctx->hash_mode),
+ HASH_LEN_SIZE);
set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
set_flow_mode(&desc[idx], S_DIN_to_HASH);
set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
@@ -782,17 +833,20 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1);
if (unlikely(rc != -EINPROGRESS)) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
ssi_hash_unmap_result(dev, state, digestsize, result);
}
} else {
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0);
if (rc != 0) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
ssi_hash_unmap_result(dev, state, digestsize, result);
} else {
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, false);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ false);
ssi_hash_unmap_result(dev, state, digestsize, result);
ssi_hash_unmap_request(dev, state, ctx);
}
@@ -804,9 +858,7 @@ static int ssi_hash_final(struct ahash_req_ctx *state,
struct ssi_hash_ctx *ctx,
unsigned int digestsize,
struct scatterlist *src,
- unsigned int nbytes,
- u8 *result,
- void *async_req)
+ unsigned int nbytes, u8 *result, void *async_req)
{
struct device *dev = &ctx->drvdata->plat_dev->dev;
bool is_hmac = ctx->is_hmac;
@@ -815,9 +867,12 @@ static int ssi_hash_final(struct ahash_req_ctx *state,
int idx = 0;
int rc;
- SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
+ SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac ? "hmac" : "hash",
+ nbytes);
- if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 0) != 0)) {
+ if (unlikely
+ (ssi_buffer_mgr_map_hash_request_final
+ (ctx->drvdata, state, src, nbytes, 0) != 0)) {
SSI_LOG_ERR("map_ahash_request_final() failed\n");
return -ENOMEM;
}
@@ -888,8 +943,9 @@ static int ssi_hash_final(struct ahash_req_ctx *state,
hw_desc_init(&desc[idx]);
set_cipher_mode(&desc[idx], ctx->hw_mode);
set_din_sram(&desc[idx],
- ssi_ahash_get_initial_digest_len_sram_addr(
-ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
+ ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata,
+ ctx->hash_mode),
+ HASH_LEN_SIZE);
set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
set_flow_mode(&desc[idx], S_DIN_to_HASH);
set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
@@ -926,17 +982,20 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1);
if (unlikely(rc != -EINPROGRESS)) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
ssi_hash_unmap_result(dev, state, digestsize, result);
}
} else {
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0);
if (rc != 0) {
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, true);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ true);
ssi_hash_unmap_result(dev, state, digestsize, result);
} else {
- ssi_buffer_mgr_unmap_hash_request(dev, state, src, false);
+ ssi_buffer_mgr_unmap_hash_request(dev, state, src,
+ false);
ssi_hash_unmap_result(dev, state, digestsize, result);
ssi_hash_unmap_request(dev, state, ctx);
}
@@ -957,8 +1016,7 @@ static int ssi_hash_init(struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx)
static int ssi_hash_setkey(void *hash,
const u8 *key,
- unsigned int keylen,
- bool synchronize)
+ unsigned int keylen, bool synchronize)
{
unsigned int hmac_pad_const[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST };
struct ssi_crypto_req ssi_req = {};
@@ -969,14 +1027,15 @@ static int ssi_hash_setkey(void *hash,
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
ssi_sram_addr_t larval_addr;
- SSI_LOG_DEBUG("start keylen: %d", keylen);
+ SSI_LOG_DEBUG("start keylen: %d", keylen);
ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash));
- blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash *)hash)->base);
+ blocksize =
+ crypto_tfm_alg_blocksize(&((struct crypto_ahash *)hash)->base);
digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash));
- larval_addr = ssi_ahash_get_larval_digest_sram_addr(
- ctx->drvdata, ctx->hash_mode);
+ larval_addr =
+ ssi_ahash_get_larval_digest_sram_addr(ctx->drvdata, ctx->hash_mode);
/* The keylen value distinguishes HASH in case keylen is ZERO bytes,
* any NON-ZERO value utilizes HMAC flow
@@ -986,19 +1045,21 @@ static int ssi_hash_setkey(void *hash,
ctx->is_hmac = true;
if (keylen != 0) {
- ctx->key_params.key_dma_addr = dma_map_single(
- &ctx->drvdata->plat_dev->dev,
- (void *)key,
- keylen, DMA_TO_DEVICE);
- if (unlikely(dma_mapping_error(&ctx->drvdata->plat_dev->dev,
- ctx->key_params.key_dma_addr))) {
- SSI_LOG_ERR("Mapping key va=0x%p len=%u for DMA failed\n",
- key, keylen);
+ ctx->key_params.key_dma_addr =
+ dma_map_single(&ctx->drvdata->plat_dev->dev, (void *)key,
+ keylen, DMA_TO_DEVICE);
+ if (unlikely
+ (dma_mapping_error
+ (&ctx->drvdata->plat_dev->dev,
+ ctx->key_params.key_dma_addr))) {
+ SSI_LOG_ERR
+ ("Mapping key va=0x%p len=%u for DMA failed\n", key,
+ keylen);
return -ENOMEM;
}
- SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
- &ctx->key_params.key_dma_addr,
- ctx->key_params.keylen);
+ SSI_LOG_DEBUG
+ ("mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
+ &ctx->key_params.key_dma_addr, ctx->key_params.keylen);
if (keylen > blocksize) {
/* Load hash initial state */
@@ -1134,15 +1195,16 @@ static int ssi_hash_setkey(void *hash,
out:
if (rc)
- crypto_ahash_set_flags((struct crypto_ahash *)hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ crypto_ahash_set_flags((struct crypto_ahash *)hash,
+ CRYPTO_TFM_RES_BAD_KEY_LEN);
if (ctx->key_params.key_dma_addr) {
dma_unmap_single(&ctx->drvdata->plat_dev->dev,
ctx->key_params.key_dma_addr,
ctx->key_params.keylen, DMA_TO_DEVICE);
- SSI_LOG_DEBUG("Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n",
- &ctx->key_params.key_dma_addr,
- ctx->key_params.keylen);
+ SSI_LOG_DEBUG
+ ("Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n",
+ &ctx->key_params.key_dma_addr, ctx->key_params.keylen);
}
return rc;
}
@@ -1168,19 +1230,18 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
ctx->key_params.keylen = keylen;
- ctx->key_params.key_dma_addr = dma_map_single(
- &ctx->drvdata->plat_dev->dev,
- (void *)key,
- keylen, DMA_TO_DEVICE);
- if (unlikely(dma_mapping_error(&ctx->drvdata->plat_dev->dev,
- ctx->key_params.key_dma_addr))) {
- SSI_LOG_ERR("Mapping key va=0x%p len=%u for DMA failed\n",
- key, keylen);
+ ctx->key_params.key_dma_addr =
+ dma_map_single(&ctx->drvdata->plat_dev->dev, (void *)key, keylen,
+ DMA_TO_DEVICE);
+ if (unlikely
+ (dma_mapping_error
+ (&ctx->drvdata->plat_dev->dev, ctx->key_params.key_dma_addr))) {
+ SSI_LOG_ERR("Mapping key va=0x%p len=%u for DMA failed\n", key,
+ keylen);
return -ENOMEM;
}
SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad keylen=%u\n",
- &ctx->key_params.key_dma_addr,
- ctx->key_params.keylen);
+ &ctx->key_params.key_dma_addr, ctx->key_params.keylen);
ctx->is_hmac = true;
/* 1. Load the AES key */
@@ -1198,24 +1259,24 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
set_din_const(&desc[idx], 0x01010101, CC_AES_128_BIT_KEY_SIZE);
set_flow_mode(&desc[idx], DIN_AES_DOUT);
set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr +
- XCBC_MAC_K1_OFFSET),
- CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0);
+ XCBC_MAC_K1_OFFSET),
+ CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0);
idx++;
hw_desc_init(&desc[idx]);
set_din_const(&desc[idx], 0x02020202, CC_AES_128_BIT_KEY_SIZE);
set_flow_mode(&desc[idx], DIN_AES_DOUT);
set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr +
- XCBC_MAC_K2_OFFSET),
- CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0);
+ XCBC_MAC_K2_OFFSET),
+ CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0);
idx++;
hw_desc_init(&desc[idx]);
set_din_const(&desc[idx], 0x03030303, CC_AES_128_BIT_KEY_SIZE);
set_flow_mode(&desc[idx], DIN_AES_DOUT);
set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr +
- XCBC_MAC_K3_OFFSET),
- CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0);
+ XCBC_MAC_K3_OFFSET),
+ CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0);
idx++;
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0);
@@ -1227,8 +1288,7 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
ctx->key_params.key_dma_addr,
ctx->key_params.keylen, DMA_TO_DEVICE);
SSI_LOG_DEBUG("Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n",
- &ctx->key_params.key_dma_addr,
- ctx->key_params.keylen);
+ &ctx->key_params.key_dma_addr, ctx->key_params.keylen);
return rc;
}
@@ -1262,7 +1322,8 @@ static int ssi_cmac_setkey(struct crypto_ahash *ahash,
memcpy(ctx->opad_tmp_keys_buff, key, keylen);
if (keylen == 24)
- memset(ctx->opad_tmp_keys_buff + 24, 0, CC_AES_KEY_SIZE_MAX - 24);
+ memset(ctx->opad_tmp_keys_buff + 24, 0,
+ CC_AES_KEY_SIZE_MAX - 24);
dma_sync_single_for_device(&ctx->drvdata->plat_dev->dev,
ctx->opad_tmp_keys_dma_addr,
@@ -1281,16 +1342,18 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx)
if (ctx->digest_buff_dma_addr != 0) {
dma_unmap_single(dev, ctx->digest_buff_dma_addr,
sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n",
- &ctx->digest_buff_dma_addr);
+ SSI_LOG_DEBUG
+ ("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n",
+ &ctx->digest_buff_dma_addr);
ctx->digest_buff_dma_addr = 0;
}
if (ctx->opad_tmp_keys_dma_addr != 0) {
dma_unmap_single(dev, ctx->opad_tmp_keys_dma_addr,
sizeof(ctx->opad_tmp_keys_buff),
DMA_BIDIRECTIONAL);
- SSI_LOG_DEBUG("Unmapped opad-digest: opad_tmp_keys_dma_addr=%pad\n",
- &ctx->opad_tmp_keys_dma_addr);
+ SSI_LOG_DEBUG
+ ("Unmapped opad-digest: opad_tmp_keys_dma_addr=%pad\n",
+ &ctx->opad_tmp_keys_dma_addr);
ctx->opad_tmp_keys_dma_addr = 0;
}
@@ -1303,21 +1366,26 @@ static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx)
ctx->key_params.keylen = 0;
- ctx->digest_buff_dma_addr = dma_map_single(dev, (void *)ctx->digest_buff, sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL);
+ ctx->digest_buff_dma_addr =
+ dma_map_single(dev, (void *)ctx->digest_buff,
+ sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL);
if (dma_mapping_error(dev, ctx->digest_buff_dma_addr)) {
- SSI_LOG_ERR("Mapping digest len %zu B at va=%pK for DMA failed\n",
- sizeof(ctx->digest_buff), ctx->digest_buff);
+ SSI_LOG_ERR
+ ("Mapping digest len %zu B at va=%pK for DMA failed\n",
+ sizeof(ctx->digest_buff), ctx->digest_buff);
goto fail;
}
SSI_LOG_DEBUG("Mapped digest %zu B at va=%pK to dma=%pad\n",
sizeof(ctx->digest_buff), ctx->digest_buff,
&ctx->digest_buff_dma_addr);
- ctx->opad_tmp_keys_dma_addr = dma_map_single(dev, (void *)ctx->opad_tmp_keys_buff, sizeof(ctx->opad_tmp_keys_buff), DMA_BIDIRECTIONAL);
+ ctx->opad_tmp_keys_dma_addr =
+ dma_map_single(dev, (void *)ctx->opad_tmp_keys_buff,
+ sizeof(ctx->opad_tmp_keys_buff), DMA_BIDIRECTIONAL);
if (dma_mapping_error(dev, ctx->opad_tmp_keys_dma_addr)) {
- SSI_LOG_ERR("Mapping opad digest %zu B at va=%pK for DMA failed\n",
- sizeof(ctx->opad_tmp_keys_buff),
- ctx->opad_tmp_keys_buff);
+ SSI_LOG_ERR
+ ("Mapping opad digest %zu B at va=%pK for DMA failed\n",
+ sizeof(ctx->opad_tmp_keys_buff), ctx->opad_tmp_keys_buff);
goto fail;
}
SSI_LOG_DEBUG("Mapped opad_tmp_keys %zu B at va=%pK to dma=%pad\n",
@@ -1336,11 +1404,11 @@ static int ssi_ahash_cra_init(struct crypto_tfm *tfm)
{
struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm);
struct hash_alg_common *hash_alg_common =
- container_of(tfm->__crt_alg, struct hash_alg_common, base);
+ container_of(tfm->__crt_alg, struct hash_alg_common, base);
struct ahash_alg *ahash_alg =
- container_of(hash_alg_common, struct ahash_alg, halg);
+ container_of(hash_alg_common, struct ahash_alg, halg);
struct ssi_hash_alg *ssi_alg =
- container_of(ahash_alg, struct ssi_hash_alg, ahash_alg);
+ container_of(ahash_alg, struct ssi_hash_alg, ahash_alg);
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
sizeof(struct ahash_req_ctx));
@@ -1380,7 +1448,9 @@ static int ssi_mac_update(struct ahash_request *req)
state->xcbc_count++;
- rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state, req->src, req->nbytes, block_size);
+ rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state,
+ req->src, req->nbytes,
+ block_size);
if (unlikely(rc)) {
if (rc == 1) {
SSI_LOG_DEBUG(" data size not require HW update %x\n",
@@ -1434,21 +1504,22 @@ static int ssi_mac_final(struct ahash_request *req)
u32 key_size, key_len;
u32 digestsize = crypto_ahash_digestsize(tfm);
- u32 rem_cnt = state->buff_index ? state->buff1_cnt :
- state->buff0_cnt;
+ u32 rem_cnt = state->buff_index ? state->buff1_cnt : state->buff0_cnt;
if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) {
key_size = CC_AES_128_BIT_KEY_SIZE;
- key_len = CC_AES_128_BIT_KEY_SIZE;
+ key_len = CC_AES_128_BIT_KEY_SIZE;
} else {
key_size = (ctx->key_params.keylen == 24) ? AES_MAX_KEY_SIZE :
- ctx->key_params.keylen;
- key_len = ctx->key_params.keylen;
+ ctx->key_params.keylen;
+ key_len = ctx->key_params.keylen;
}
SSI_LOG_DEBUG("===== final xcbc reminder (%d) ====\n", rem_cnt);
- if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 0) != 0)) {
+ if (unlikely
+ (ssi_buffer_mgr_map_hash_request_final
+ (ctx->drvdata, state, req->src, req->nbytes, 0) != 0)) {
SSI_LOG_ERR("map_ahash_request_final() failed\n");
return -ENOMEM;
}
@@ -1504,7 +1575,8 @@ static int ssi_mac_final(struct ahash_request *req)
set_flow_mode(&desc[idx], S_DIN_to_AES);
idx++;
} else if (rem_cnt > 0) {
- ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);
+ ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false,
+ &idx);
} else {
hw_desc_init(&desc[idx]);
set_din_const(&desc[idx], 0x00, CC_AES_BLOCK_SIZE);
@@ -1551,7 +1623,9 @@ static int ssi_mac_finup(struct ahash_request *req)
return ssi_mac_final(req);
}
- if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) {
+ if (unlikely
+ (ssi_buffer_mgr_map_hash_request_final
+ (ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) {
SSI_LOG_ERR("map_ahash_request_final() failed\n");
return -ENOMEM;
}
@@ -1580,7 +1654,8 @@ static int ssi_mac_finup(struct ahash_request *req)
set_flow_mode(&desc[idx], S_DIN_to_AES);
idx++;
} else {
- ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);
+ ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false,
+ &idx);
}
/* Get final MAC result */
@@ -1616,7 +1691,7 @@ static int ssi_mac_digest(struct ahash_request *req)
int idx = 0;
int rc;
- SSI_LOG_DEBUG("===== -digest mac (%d) ====\n", req->nbytes);
+ SSI_LOG_DEBUG("===== -digest mac (%d) ====\n", req->nbytes);
if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) {
SSI_LOG_ERR("map_ahash_source() failed\n");
@@ -1627,7 +1702,9 @@ static int ssi_mac_digest(struct ahash_request *req)
return -ENOMEM;
}
- if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) {
+ if (unlikely
+ (ssi_buffer_mgr_map_hash_request_final
+ (ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) {
SSI_LOG_ERR("map_ahash_request_final() failed\n");
return -ENOMEM;
}
@@ -1652,7 +1729,8 @@ static int ssi_mac_digest(struct ahash_request *req)
set_flow_mode(&desc[idx], S_DIN_to_AES);
idx++;
} else {
- ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);
+ ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false,
+ &idx);
}
/* Get final MAC result */
@@ -1684,7 +1762,8 @@ static int ssi_ahash_digest(struct ahash_request *req)
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm);
u32 digestsize = crypto_ahash_digestsize(tfm);
- return ssi_hash_digest(state, ctx, digestsize, req->src, req->nbytes, req->result, (void *)req);
+ return ssi_hash_digest(state, ctx, digestsize, req->src, req->nbytes,
+ req->result, (void *)req);
}
static int ssi_ahash_update(struct ahash_request *req)
@@ -1694,7 +1773,8 @@ static int ssi_ahash_update(struct ahash_request *req)
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm);
unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base);
- return ssi_hash_update(state, ctx, block_size, req->src, req->nbytes, (void *)req);
+ return ssi_hash_update(state, ctx, block_size, req->src, req->nbytes,
+ (void *)req);
}
static int ssi_ahash_finup(struct ahash_request *req)
@@ -1704,7 +1784,8 @@ static int ssi_ahash_finup(struct ahash_request *req)
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm);
u32 digestsize = crypto_ahash_digestsize(tfm);
- return ssi_hash_finup(state, ctx, digestsize, req->src, req->nbytes, req->result, (void *)req);
+ return ssi_hash_finup(state, ctx, digestsize, req->src, req->nbytes,
+ req->result, (void *)req);
}
static int ssi_ahash_final(struct ahash_request *req)
@@ -1714,7 +1795,8 @@ static int ssi_ahash_final(struct ahash_request *req)
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm);
u32 digestsize = crypto_ahash_digestsize(tfm);
- return ssi_hash_final(state, ctx, digestsize, req->src, req->nbytes, req->result, (void *)req);
+ return ssi_hash_final(state, ctx, digestsize, req->src, req->nbytes,
+ req->result, (void *)req);
}
static int ssi_ahash_init(struct ahash_request *req)
@@ -1736,7 +1818,7 @@ static int ssi_ahash_export(struct ahash_request *req, void *out)
struct ahash_req_ctx *state = ahash_request_ctx(req);
u8 *curr_buff = state->buff_index ? state->buff1 : state->buff0;
u32 curr_buff_cnt = state->buff_index ? state->buff1_cnt :
- state->buff0_cnt;
+ state->buff0_cnt;
const u32 tmp = CC_EXPORT_MAGIC;
memcpy(out, &tmp, sizeof(u32));
@@ -1848,7 +1930,6 @@ struct ssi_hash_template {
#define CC_STATE_SIZE(_x) \
((_x) + HASH_LEN_SIZE + SSI_MAX_HASH_BLCK_SIZE + (2 * sizeof(u32)))
-
/* hash descriptors */
static struct ssi_hash_template driver_hash[] = {
//Asynchronize hash template
@@ -2048,8 +2129,8 @@ static struct ssi_hash_template driver_hash[] = {
};
-static struct ssi_hash_alg *
-ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed)
+static struct ssi_hash_alg *ssi_hash_create_alg(struct ssi_hash_template
+ *template, bool keyed)
{
struct ssi_hash_alg *t_crypto_alg;
struct crypto_alg *alg;
@@ -2086,7 +2167,7 @@ ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed)
alg->cra_init = ssi_ahash_cra_init;
alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH |
- CRYPTO_ALG_KERN_DRIVER_ONLY;
+ CRYPTO_ALG_KERN_DRIVER_ONLY;
alg->cra_type = &crypto_ahash_type;
t_crypto_alg->hash_mode = template->hash_mode;
@@ -2234,14 +2315,11 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata)
sram_size_to_alloc = sizeof(digest_len_init) +
#if (DX_DEV_SHA_MAX > 256)
- sizeof(digest_len_sha512_init) +
- sizeof(sha384_init) +
- sizeof(sha512_init) +
+ sizeof(digest_len_sha512_init) +
+ sizeof(sha384_init) + sizeof(sha512_init) +
#endif
- sizeof(md5_init) +
- sizeof(sha1_init) +
- sizeof(sha224_init) +
- sizeof(sha256_init);
+ sizeof(md5_init) +
+ sizeof(sha1_init) + sizeof(sha224_init) + sizeof(sha256_init);
sram_buff = ssi_sram_mgr_alloc(drvdata, sram_size_to_alloc);
if (sram_buff == NULL_SRAM_ADDR) {
@@ -2282,8 +2360,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata)
kfree(t_alg);
goto fail;
} else {
- list_add_tail(&t_alg->entry,
- &hash_handle->hash_list);
+ list_add_tail(&t_alg->entry, &hash_handle->hash_list);
}
if ((hw_mode == DRV_CIPHER_XCBC_MAC) ||
@@ -2325,7 +2402,8 @@ int ssi_hash_free(struct ssi_drvdata *drvdata)
struct ssi_hash_handle *hash_handle = drvdata->hash_handle;
if (hash_handle) {
- list_for_each_entry_safe(t_hash_alg, hash_n, &hash_handle->hash_list, entry) {
+ list_for_each_entry_safe(t_hash_alg, hash_n,
+ &hash_handle->hash_list, entry) {
crypto_unregister_ahash(&t_hash_alg->ahash_alg);
list_del(&t_hash_alg->entry);
kfree(t_hash_alg);
@@ -2490,7 +2568,7 @@ ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode)
switch (mode) {
case DRV_HASH_NULL:
- break; /*Ignore*/
+ break; /*Ignore */
case DRV_HASH_MD5:
return (hash_handle->larval_digest_sram_addr);
case DRV_HASH_SHA1:
@@ -2498,27 +2576,23 @@ ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode)
sizeof(md5_init));
case DRV_HASH_SHA224:
return (hash_handle->larval_digest_sram_addr +
- sizeof(md5_init) +
- sizeof(sha1_init));
+ sizeof(md5_init) + sizeof(sha1_init));
case DRV_HASH_SHA256:
return (hash_handle->larval_digest_sram_addr +
sizeof(md5_init) +
- sizeof(sha1_init) +
- sizeof(sha224_init));
+ sizeof(sha1_init) + sizeof(sha224_init));
#if (DX_DEV_SHA_MAX > 256)
case DRV_HASH_SHA384:
return (hash_handle->larval_digest_sram_addr +
sizeof(md5_init) +
sizeof(sha1_init) +
- sizeof(sha224_init) +
- sizeof(sha256_init));
+ sizeof(sha224_init) + sizeof(sha256_init));
case DRV_HASH_SHA512:
return (hash_handle->larval_digest_sram_addr +
sizeof(md5_init) +
sizeof(sha1_init) +
sizeof(sha224_init) +
- sizeof(sha256_init) +
- sizeof(sha384_init));
+ sizeof(sha256_init) + sizeof(sha384_init));
#endif
default:
SSI_LOG_ERR("Invalid hash mode (%d)\n", mode);
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 14/22] staging: ccree: fix struct init braces
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (12 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 13/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 15/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
` (8 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Put struct init braces on line of it's own.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_hash.c | 32 ++++++++++++++++++++++++--------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index e2dc5d8..6baa449 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -41,26 +41,42 @@ struct ssi_hash_handle {
};
static const u32 digest_len_init[] = {
- 0x00000040, 0x00000000, 0x00000000, 0x00000000 };
+ 0x00000040, 0x00000000, 0x00000000, 0x00000000
+};
+
static const u32 md5_init[] = {
- SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };
+ SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0
+};
+
static const u32 sha1_init[] = {
- SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };
+ SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0
+};
+
static const u32 sha224_init[] = {
SHA224_H7, SHA224_H6, SHA224_H5, SHA224_H4,
- SHA224_H3, SHA224_H2, SHA224_H1, SHA224_H0 };
+ SHA224_H3, SHA224_H2, SHA224_H1, SHA224_H0
+};
+
static const u32 sha256_init[] = {
SHA256_H7, SHA256_H6, SHA256_H5, SHA256_H4,
- SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0 };
+ SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0
+};
+
#if (DX_DEV_SHA_MAX > 256)
static const u32 digest_len_sha512_init[] = {
- 0x00000080, 0x00000000, 0x00000000, 0x00000000 };
+ 0x00000080, 0x00000000, 0x00000000, 0x00000000
+};
+
static const u64 sha384_init[] = {
SHA384_H7, SHA384_H6, SHA384_H5, SHA384_H4,
- SHA384_H3, SHA384_H2, SHA384_H1, SHA384_H0 };
+ SHA384_H3, SHA384_H2, SHA384_H1, SHA384_H0
+};
+
static const u64 sha512_init[] = {
SHA512_H7, SHA512_H6, SHA512_H5, SHA512_H4,
- SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 };
+ SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0
+};
+
#endif
static void ssi_hash_create_xcbc_setup(struct ahash_request *areq,
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 15/22] staging: ccree: fix line indentation and breaks
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (13 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 14/22] staging: ccree: fix struct init braces Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 16/22] staging: ccree: fix spelling mistakes Gilad Ben-Yossef
` (7 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Fix source line indentation and breaks in ssi_aead.c
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_aead.c | 1024 ++++++++++++++++++++------------------
1 file changed, 532 insertions(+), 492 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 03533c8..515a603 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -101,7 +101,8 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
dev = &ctx->drvdata->plat_dev->dev;
/* Unmap enckey buffer */
if (ctx->enckey) {
- dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, ctx->enckey_dma_addr);
+ dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey,
+ ctx->enckey_dma_addr);
SSI_LOG_DEBUG("Freed enckey DMA buffer enckey_dma_addr=%pad\n",
&ctx->enckey_dma_addr);
ctx->enckey_dma_addr = 0;
@@ -116,8 +117,9 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
xcbc->xcbc_keys,
xcbc->xcbc_keys_dma_addr);
}
- SSI_LOG_DEBUG("Freed xcbc_keys DMA buffer xcbc_keys_dma_addr=%pad\n",
- &xcbc->xcbc_keys_dma_addr);
+ SSI_LOG_DEBUG
+ ("Freed xcbc_keys DMA buffer xcbc_keys_dma_addr=%pad\n",
+ &xcbc->xcbc_keys_dma_addr);
xcbc->xcbc_keys_dma_addr = 0;
xcbc->xcbc_keys = NULL;
} else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */
@@ -127,8 +129,9 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
dma_free_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE,
hmac->ipad_opad,
hmac->ipad_opad_dma_addr);
- SSI_LOG_DEBUG("Freed ipad_opad DMA buffer ipad_opad_dma_addr=%pad\n",
- &hmac->ipad_opad_dma_addr);
+ SSI_LOG_DEBUG
+ ("Freed ipad_opad DMA buffer ipad_opad_dma_addr=%pad\n",
+ &hmac->ipad_opad_dma_addr);
hmac->ipad_opad_dma_addr = 0;
hmac->ipad_opad = NULL;
}
@@ -136,8 +139,9 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
dma_free_coherent(dev, MAX_HMAC_BLOCK_SIZE,
hmac->padded_authkey,
hmac->padded_authkey_dma_addr);
- SSI_LOG_DEBUG("Freed padded_authkey DMA buffer padded_authkey_dma_addr=%pad\n",
- &hmac->padded_authkey_dma_addr);
+ SSI_LOG_DEBUG
+ ("Freed padded_authkey DMA buffer padded_authkey_dma_addr=%pad\n",
+ &hmac->padded_authkey_dma_addr);
hmac->padded_authkey_dma_addr = 0;
hmac->padded_authkey = NULL;
}
@@ -150,8 +154,9 @@ static int ssi_aead_init(struct crypto_aead *tfm)
struct aead_alg *alg = crypto_aead_alg(tfm);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct ssi_crypto_alg *ssi_alg =
- container_of(alg, struct ssi_crypto_alg, aead_alg);
- SSI_LOG_DEBUG("Initializing context @%p for %s\n", ctx, crypto_tfm_alg_name(&tfm->base));
+ container_of(alg, struct ssi_crypto_alg, aead_alg);
+ SSI_LOG_DEBUG("Initializing context @%p for %s\n", ctx,
+ crypto_tfm_alg_name(&tfm->base));
/* Initialize modes in instance */
ctx->cipher_mode = ssi_alg->cipher_mode;
@@ -168,7 +173,8 @@ static int ssi_aead_init(struct crypto_aead *tfm)
SSI_LOG_ERR("Failed allocating key buffer\n");
goto init_failed;
}
- SSI_LOG_DEBUG("Allocated enckey buffer in context ctx->enckey=@%p\n", ctx->enckey);
+ SSI_LOG_DEBUG("Allocated enckey buffer in context ctx->enckey=@%p\n",
+ ctx->enckey);
/* Set default authlen value */
@@ -200,13 +206,13 @@ static int ssi_aead_init(struct crypto_aead *tfm)
goto init_failed;
}
- SSI_LOG_DEBUG("Allocated authkey buffer in context ctx->authkey=@%p\n",
- hmac->ipad_opad);
+ SSI_LOG_DEBUG
+ ("Allocated authkey buffer in context ctx->authkey=@%p\n",
+ hmac->ipad_opad);
hmac->padded_authkey = dma_alloc_coherent(dev,
MAX_HMAC_BLOCK_SIZE,
- pkey_dma,
- GFP_KERNEL);
+ pkey_dma, GFP_KERNEL);
if (!hmac->padded_authkey) {
SSI_LOG_ERR("failed to allocate padded_authkey\n");
@@ -224,7 +230,8 @@ static int ssi_aead_init(struct crypto_aead *tfm)
return -ENOMEM;
}
-static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *cc_base)
+static void ssi_aead_complete(struct device *dev, void *ssi_req,
+ void __iomem *cc_base)
{
struct aead_request *areq = (struct aead_request *)ssi_req;
struct aead_req_ctx *areq_ctx = aead_request_ctx(areq);
@@ -240,8 +247,9 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c
if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
if (memcmp(areq_ctx->mac_buf, areq_ctx->icv_virt_addr,
ctx->authsize) != 0) {
- SSI_LOG_DEBUG("Payload authentication failure, (auth-size=%d, cipher=%d).\n",
- ctx->authsize, ctx->cipher_mode);
+ SSI_LOG_DEBUG
+ ("Payload authentication failure, (auth-size=%d, cipher=%d).\n",
+ ctx->authsize, ctx->cipher_mode);
/* In case of payload authentication failure, MUST NOT
* revealed the decrypted message --> zero its memory.
*/
@@ -250,16 +258,26 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c
}
} else { /*ENCRYPT*/
if (unlikely(areq_ctx->is_icv_fragmented))
- ssi_buffer_mgr_copy_scatterlist_portion(
- areq_ctx->mac_buf, areq_ctx->dst_sgl, areq->cryptlen + areq_ctx->dst_offset,
- areq->cryptlen + areq_ctx->dst_offset + ctx->authsize, SSI_SG_FROM_BUF);
+ ssi_buffer_mgr_copy_scatterlist_portion(areq_ctx->mac_buf,
+ areq_ctx->dst_sgl,
+ areq->cryptlen +
+ areq_ctx->dst_offset,
+ areq->cryptlen +
+ areq_ctx->dst_offset +
+ ctx->authsize,
+ SSI_SG_FROM_BUF);
/* If an IV was generated, copy it back to the user provided buffer. */
if (areq_ctx->backup_giv) {
if (ctx->cipher_mode == DRV_CIPHER_CTR)
- memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv + CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_IV_SIZE);
+ memcpy(areq_ctx->backup_giv,
+ areq_ctx->ctr_iv +
+ CTR_RFC3686_NONCE_SIZE,
+ CTR_RFC3686_IV_SIZE);
else if (ctx->cipher_mode == DRV_CIPHER_CCM)
- memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET, CCM_BLOCK_IV_SIZE);
+ memcpy(areq_ctx->backup_giv,
+ areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET,
+ CCM_BLOCK_IV_SIZE);
}
}
@@ -292,15 +310,15 @@ static int xcbc_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx)
set_din_const(&desc[2], 0x02020202, CC_AES_128_BIT_KEY_SIZE);
set_flow_mode(&desc[2], DIN_AES_DOUT);
set_dout_dlli(&desc[2], (ctx->auth_state.xcbc.xcbc_keys_dma_addr
- + AES_KEYSIZE_128),
- AES_KEYSIZE_128, NS_BIT, 0);
+ + AES_KEYSIZE_128),
+ AES_KEYSIZE_128, NS_BIT, 0);
hw_desc_init(&desc[3]);
set_din_const(&desc[3], 0x03030303, CC_AES_128_BIT_KEY_SIZE);
set_flow_mode(&desc[3], DIN_AES_DOUT);
set_dout_dlli(&desc[3], (ctx->auth_state.xcbc.xcbc_keys_dma_addr
- + 2 * AES_KEYSIZE_128),
- AES_KEYSIZE_128, NS_BIT, 0);
+ + 2 * AES_KEYSIZE_128),
+ AES_KEYSIZE_128, NS_BIT, 0);
return 4;
}
@@ -310,9 +328,9 @@ static int hmac_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx)
unsigned int hmac_pad_const[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST };
unsigned int digest_ofs = 0;
unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
- DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
+ DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ?
- CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
+ CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
struct cc_hmac_s *hmac = &ctx->auth_state.hmac;
int idx = 0;
@@ -324,8 +342,8 @@ static int hmac_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx)
hw_desc_init(&desc[idx]);
set_cipher_mode(&desc[idx], hash_mode);
set_din_sram(&desc[idx],
- ssi_ahash_get_larval_digest_sram_addr(
- ctx->drvdata, ctx->auth_mode),
+ ssi_ahash_get_larval_digest_sram_addr(ctx->drvdata,
+ ctx->auth_mode),
digest_size);
set_flow_mode(&desc[idx], S_DIN_to_HASH);
set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
@@ -421,13 +439,14 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx)
* (copy to intenral buffer or hash in case of key longer than block
*/
static int
-ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
+ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key,
+ unsigned int keylen)
{
dma_addr_t key_dma_addr = 0;
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct device *dev = &ctx->drvdata->plat_dev->dev;
- u32 larval_addr = ssi_ahash_get_larval_digest_sram_addr(
- ctx->drvdata, ctx->auth_mode);
+ u32 larval_addr =
+ ssi_ahash_get_larval_digest_sram_addr(ctx->drvdata, ctx->auth_mode);
struct ssi_crypto_req ssi_req = {};
unsigned int blocksize;
unsigned int digestsize;
@@ -436,9 +455,9 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl
int rc = 0;
struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ];
dma_addr_t padded_authkey_dma_addr =
- ctx->auth_state.hmac.padded_authkey_dma_addr;
+ ctx->auth_state.hmac.padded_authkey_dma_addr;
- switch (ctx->auth_mode) { /* auth_key required and >0 */
+ switch (ctx->auth_mode) { /* auth_key required and >0 */
case DRV_HASH_SHA1:
blocksize = SHA1_BLOCK_SIZE;
digestsize = SHA1_DIGEST_SIZE;
@@ -452,10 +471,12 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl
}
if (likely(keylen != 0)) {
- key_dma_addr = dma_map_single(dev, (void *)key, keylen, DMA_TO_DEVICE);
+ key_dma_addr =
+ dma_map_single(dev, (void *)key, keylen, DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, key_dma_addr))) {
- SSI_LOG_ERR("Mapping key va=0x%p len=%u for DMA failed\n",
- key, keylen);
+ SSI_LOG_ERR
+ ("Mapping key va=0x%p len=%u for DMA failed\n", key,
+ keylen);
return -ENOMEM;
}
if (keylen > blocksize) {
@@ -498,8 +519,8 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl
set_din_const(&desc[idx], 0, (blocksize - digestsize));
set_flow_mode(&desc[idx], BYPASS);
set_dout_dlli(&desc[idx], (padded_authkey_dma_addr +
- digestsize), (blocksize - digestsize),
- NS_BIT, 0);
+ digestsize),
+ (blocksize - digestsize), NS_BIT, 0);
idx++;
} else {
hw_desc_init(&desc[idx]);
@@ -580,8 +601,9 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
/* Copy nonce from last 4 bytes in CTR key to
* first 4 bytes in CTR IV
*/
- memcpy(ctx->ctr_nonce, key + ctx->auth_keylen + ctx->enc_keylen -
- CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_NONCE_SIZE);
+ memcpy(ctx->ctr_nonce,
+ key + ctx->auth_keylen + ctx->enc_keylen -
+ CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_NONCE_SIZE);
/* Set CTR key size */
ctx->enc_keylen -= CTR_RFC3686_NONCE_SIZE;
}
@@ -647,7 +669,8 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
}
#if SSI_CC_HAS_AES_CCM
-static int ssi_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
+static int ssi_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key,
+ unsigned int keylen)
{
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
int rc = 0;
@@ -664,17 +687,14 @@ static int ssi_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, unsign
}
#endif /*SSI_CC_HAS_AES_CCM*/
-static int ssi_aead_setauthsize(
- struct crypto_aead *authenc,
- unsigned int authsize)
+static int ssi_aead_setauthsize(struct crypto_aead *authenc,
+ unsigned int authsize)
{
struct ssi_aead_ctx *ctx = crypto_aead_ctx(authenc);
/* Unsupported auth. sizes */
- if ((authsize == 0) ||
- (authsize > crypto_aead_maxauthsize(authenc))) {
+ if ((authsize == 0) || (authsize > crypto_aead_maxauthsize(authenc)))
return -ENOTSUPP;
- }
ctx->authsize = authsize;
SSI_LOG_DEBUG("authlen=%d\n", ctx->authsize);
@@ -719,11 +739,9 @@ static int ssi_ccm_setauthsize(struct crypto_aead *authenc,
#endif /*SSI_CC_HAS_AES_CCM*/
static inline void
-ssi_aead_create_assoc_desc(
- struct aead_request *areq,
- unsigned int flow_mode,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+ssi_aead_create_assoc_desc(struct aead_request *areq,
+ unsigned int flow_mode,
+ struct cc_hw_desc desc[], unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(areq);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -736,8 +754,8 @@ ssi_aead_create_assoc_desc(
SSI_LOG_DEBUG("ASSOC buffer type DLLI\n");
hw_desc_init(&desc[idx]);
set_din_type(&desc[idx], DMA_DLLI, sg_dma_address(areq->src),
- areq->assoclen, NS_BIT); set_flow_mode(&desc[idx],
- flow_mode);
+ areq->assoclen, NS_BIT);
+ set_flow_mode(&desc[idx], flow_mode);
if ((ctx->auth_mode == DRV_HASH_XCBC_MAC) &&
(areq_ctx->cryptlen > 0))
set_din_not_last_indication(&desc[idx]);
@@ -761,12 +779,10 @@ ssi_aead_create_assoc_desc(
}
static inline void
-ssi_aead_process_authenc_data_desc(
- struct aead_request *areq,
- unsigned int flow_mode,
- struct cc_hw_desc desc[],
- unsigned int *seq_size,
- int direct)
+ssi_aead_process_authenc_data_desc(struct aead_request *areq,
+ unsigned int flow_mode,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size, int direct)
{
struct aead_req_ctx *areq_ctx = aead_request_ctx(areq);
enum ssi_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type;
@@ -774,48 +790,48 @@ ssi_aead_process_authenc_data_desc(
switch (data_dma_type) {
case SSI_DMA_BUF_DLLI:
- {
- struct scatterlist *cipher =
- (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
- areq_ctx->dst_sgl : areq_ctx->src_sgl;
-
- unsigned int offset =
- (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
- areq_ctx->dst_offset : areq_ctx->src_offset;
- SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type DLLI\n");
- hw_desc_init(&desc[idx]);
- set_din_type(&desc[idx], DMA_DLLI,
- (sg_dma_address(cipher) + offset),
- areq_ctx->cryptlen, NS_BIT);
- set_flow_mode(&desc[idx], flow_mode);
- break;
- }
+ {
+ struct scatterlist *cipher =
+ (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
+ areq_ctx->dst_sgl : areq_ctx->src_sgl;
+
+ unsigned int offset =
+ (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
+ areq_ctx->dst_offset : areq_ctx->src_offset;
+ SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type DLLI\n");
+ hw_desc_init(&desc[idx]);
+ set_din_type(&desc[idx], DMA_DLLI,
+ (sg_dma_address(cipher) + offset),
+ areq_ctx->cryptlen, NS_BIT);
+ set_flow_mode(&desc[idx], flow_mode);
+ break;
+ }
case SSI_DMA_BUF_MLLI:
- {
- /* DOUBLE-PASS flow (as default)
- * assoc. + iv + data -compact in one table
- * if assoclen is ZERO only IV perform
- */
- ssi_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr;
- u32 mlli_nents = areq_ctx->assoc.mlli_nents;
-
- if (likely(areq_ctx->is_single_pass)) {
- if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
- mlli_addr = areq_ctx->dst.sram_addr;
- mlli_nents = areq_ctx->dst.mlli_nents;
- } else {
- mlli_addr = areq_ctx->src.sram_addr;
- mlli_nents = areq_ctx->src.mlli_nents;
+ {
+ /* DOUBLE-PASS flow (as default)
+ * assoc. + iv + data -compact in one table
+ * if assoclen is ZERO only IV perform
+ */
+ ssi_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr;
+ u32 mlli_nents = areq_ctx->assoc.mlli_nents;
+
+ if (likely(areq_ctx->is_single_pass)) {
+ if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
+ mlli_addr = areq_ctx->dst.sram_addr;
+ mlli_nents = areq_ctx->dst.mlli_nents;
+ } else {
+ mlli_addr = areq_ctx->src.sram_addr;
+ mlli_nents = areq_ctx->src.mlli_nents;
+ }
}
- }
- SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type MLLI\n");
- hw_desc_init(&desc[idx]);
- set_din_type(&desc[idx], DMA_MLLI, mlli_addr, mlli_nents,
- NS_BIT);
- set_flow_mode(&desc[idx], flow_mode);
- break;
- }
+ SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type MLLI\n");
+ hw_desc_init(&desc[idx]);
+ set_din_type(&desc[idx], DMA_MLLI, mlli_addr,
+ mlli_nents, NS_BIT);
+ set_flow_mode(&desc[idx], flow_mode);
+ break;
+ }
case SSI_DMA_BUF_NULL:
default:
SSI_LOG_ERR("AUTHENC: Invalid SRC/DST buffer type\n");
@@ -825,11 +841,10 @@ ssi_aead_process_authenc_data_desc(
}
static inline void
-ssi_aead_process_cipher_data_desc(
- struct aead_request *areq,
- unsigned int flow_mode,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+ssi_aead_process_cipher_data_desc(struct aead_request *areq,
+ unsigned int flow_mode,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
unsigned int idx = *seq_size;
struct aead_req_ctx *areq_ctx = aead_request_ctx(areq);
@@ -844,11 +859,12 @@ ssi_aead_process_cipher_data_desc(
hw_desc_init(&desc[idx]);
set_din_type(&desc[idx], DMA_DLLI,
(sg_dma_address(areq_ctx->src_sgl) +
- areq_ctx->src_offset), areq_ctx->cryptlen, NS_BIT);
+ areq_ctx->src_offset), areq_ctx->cryptlen,
+ NS_BIT);
set_dout_dlli(&desc[idx],
(sg_dma_address(areq_ctx->dst_sgl) +
- areq_ctx->dst_offset),
- areq_ctx->cryptlen, NS_BIT, 0);
+ areq_ctx->dst_offset), areq_ctx->cryptlen,
+ NS_BIT, 0);
set_flow_mode(&desc[idx], flow_mode);
break;
case SSI_DMA_BUF_MLLI:
@@ -868,17 +884,16 @@ ssi_aead_process_cipher_data_desc(
*seq_size = (++idx);
}
-static inline void ssi_aead_process_digest_result_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_process_digest_result_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
unsigned int idx = *seq_size;
unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
- DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
+ DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
int direct = req_ctx->gen_ctx.op_type;
/* Get final ICV result */
@@ -919,10 +934,9 @@ static inline void ssi_aead_process_digest_result_desc(
*seq_size = (++idx);
}
-static inline void ssi_aead_setup_cipher_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_setup_cipher_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -965,11 +979,10 @@ static inline void ssi_aead_setup_cipher_desc(
*seq_size = idx;
}
-static inline void ssi_aead_process_cipher(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size,
- unsigned int data_flow_mode)
+static inline void ssi_aead_process_cipher(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size,
+ unsigned int data_flow_mode)
{
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
int direct = req_ctx->gen_ctx.op_type;
@@ -991,17 +1004,16 @@ static inline void ssi_aead_process_cipher(
*seq_size = idx;
}
-static inline void ssi_aead_hmac_setup_digest_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_hmac_setup_digest_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
- DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
+ DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ?
- CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
+ CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
unsigned int idx = *seq_size;
/* Loading hash ipad xor key state */
@@ -1020,7 +1032,7 @@ static inline void ssi_aead_hmac_setup_digest_desc(
set_din_sram(&desc[idx],
ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata,
hash_mode),
- HASH_LEN_SIZE);
+ HASH_LEN_SIZE);
set_flow_mode(&desc[idx], S_DIN_to_HASH);
set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
idx++;
@@ -1028,10 +1040,9 @@ static inline void ssi_aead_hmac_setup_digest_desc(
*seq_size = idx;
}
-static inline void ssi_aead_xcbc_setup_digest_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_xcbc_setup_digest_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -1090,10 +1101,9 @@ static inline void ssi_aead_xcbc_setup_digest_desc(
*seq_size = idx;
}
-static inline void ssi_aead_process_digest_header_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_process_digest_header_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
unsigned int idx = *seq_size;
/* Hash associated data */
@@ -1104,18 +1114,17 @@ static inline void ssi_aead_process_digest_header_desc(
*seq_size = idx;
}
-static inline void ssi_aead_process_digest_scheme_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_process_digest_scheme_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct ssi_aead_handle *aead_handle = ctx->drvdata->aead_handle;
unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
- DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
+ DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ?
- CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
+ CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
unsigned int idx = *seq_size;
hw_desc_init(&desc[idx]);
@@ -1161,27 +1170,24 @@ static inline void ssi_aead_process_digest_scheme_desc(
/* Perform HASH update */
hw_desc_init(&desc[idx]);
- set_din_sram(&desc[idx], aead_handle->sram_workspace_addr,
- digest_size);
+ set_din_sram(&desc[idx], aead_handle->sram_workspace_addr, digest_size);
set_flow_mode(&desc[idx], DIN_HASH);
idx++;
*seq_size = idx;
}
-static inline void ssi_aead_load_mlli_to_sram(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_load_mlli_to_sram(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
- if (unlikely(
- (req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) ||
- (req_ctx->data_buff_type == SSI_DMA_BUF_MLLI) ||
- !req_ctx->is_single_pass)) {
+ if (unlikely((req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) ||
+ (req_ctx->data_buff_type == SSI_DMA_BUF_MLLI) ||
+ !req_ctx->is_single_pass)) {
SSI_LOG_DEBUG("Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n",
(unsigned int)ctx->drvdata->mlli_sram_addr,
req_ctx->mlli_params.mlli_len);
@@ -1198,43 +1204,45 @@ static inline void ssi_aead_load_mlli_to_sram(
}
}
-static inline enum cc_flow_mode ssi_aead_get_data_flow_mode(
- enum drv_crypto_direction direct,
- enum cc_flow_mode setup_flow_mode,
- bool is_single_pass)
+static inline enum cc_flow_mode ssi_aead_get_data_flow_mode(enum
+ drv_crypto_direction
+ direct,
+ enum cc_flow_mode
+ setup_flow_mode,
+ bool is_single_pass)
{
enum cc_flow_mode data_flow_mode;
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
if (setup_flow_mode == S_DIN_to_AES)
data_flow_mode = likely(is_single_pass) ?
- AES_to_HASH_and_DOUT : DIN_AES_DOUT;
+ AES_to_HASH_and_DOUT : DIN_AES_DOUT;
else
data_flow_mode = likely(is_single_pass) ?
- DES_to_HASH_and_DOUT : DIN_DES_DOUT;
+ DES_to_HASH_and_DOUT : DIN_DES_DOUT;
} else { /* Decrypt */
if (setup_flow_mode == S_DIN_to_AES)
data_flow_mode = likely(is_single_pass) ?
- AES_and_HASH : DIN_AES_DOUT;
+ AES_and_HASH : DIN_AES_DOUT;
else
data_flow_mode = likely(is_single_pass) ?
- DES_and_HASH : DIN_DES_DOUT;
+ DES_and_HASH : DIN_DES_DOUT;
}
return data_flow_mode;
}
-static inline void ssi_aead_hmac_authenc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_hmac_authenc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
int direct = req_ctx->gen_ctx.op_type;
- unsigned int data_flow_mode = ssi_aead_get_data_flow_mode(
- direct, ctx->flow_mode, req_ctx->is_single_pass);
+ unsigned int data_flow_mode =
+ ssi_aead_get_data_flow_mode(direct, ctx->flow_mode,
+ req_ctx->is_single_pass);
if (req_ctx->is_single_pass) {
/**
@@ -1243,7 +1251,8 @@ static inline void ssi_aead_hmac_authenc(
ssi_aead_hmac_setup_digest_desc(req, desc, seq_size);
ssi_aead_setup_cipher_desc(req, desc, seq_size);
ssi_aead_process_digest_header_desc(req, desc, seq_size);
- ssi_aead_process_cipher_data_desc(req, data_flow_mode, desc, seq_size);
+ ssi_aead_process_cipher_data_desc(req, data_flow_mode, desc,
+ seq_size);
ssi_aead_process_digest_scheme_desc(req, desc, seq_size);
ssi_aead_process_digest_result_desc(req, desc, seq_size);
return;
@@ -1257,16 +1266,19 @@ static inline void ssi_aead_hmac_authenc(
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
/* encrypt first.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
- /* authenc after..*/
+ /* authenc after.. */
ssi_aead_hmac_setup_digest_desc(req, desc, seq_size);
- ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc, seq_size, direct);
+ ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc,
+ seq_size, direct);
ssi_aead_process_digest_scheme_desc(req, desc, seq_size);
ssi_aead_process_digest_result_desc(req, desc, seq_size);
- } else { /*DECRYPT*/
- /* authenc first..*/
+ } else {
+ /*DECRYPT*/
+ /* authenc first.. */
ssi_aead_hmac_setup_digest_desc(req, desc, seq_size);
- ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc, seq_size, direct);
+ ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc,
+ seq_size, direct);
ssi_aead_process_digest_scheme_desc(req, desc, seq_size);
/* decrypt after.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
@@ -1278,17 +1290,16 @@ static inline void ssi_aead_hmac_authenc(
}
static inline void
-ssi_aead_xcbc_authenc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+ssi_aead_xcbc_authenc(struct aead_request *req,
+ struct cc_hw_desc desc[], unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
int direct = req_ctx->gen_ctx.op_type;
- unsigned int data_flow_mode = ssi_aead_get_data_flow_mode(
- direct, ctx->flow_mode, req_ctx->is_single_pass);
+ unsigned int data_flow_mode =
+ ssi_aead_get_data_flow_mode(direct, ctx->flow_mode,
+ req_ctx->is_single_pass);
if (req_ctx->is_single_pass) {
/**
@@ -1297,7 +1308,8 @@ ssi_aead_xcbc_authenc(
ssi_aead_xcbc_setup_digest_desc(req, desc, seq_size);
ssi_aead_setup_cipher_desc(req, desc, seq_size);
ssi_aead_process_digest_header_desc(req, desc, seq_size);
- ssi_aead_process_cipher_data_desc(req, data_flow_mode, desc, seq_size);
+ ssi_aead_process_cipher_data_desc(req, data_flow_mode, desc,
+ seq_size);
ssi_aead_process_digest_result_desc(req, desc, seq_size);
return;
}
@@ -1312,13 +1324,16 @@ ssi_aead_xcbc_authenc(
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
/* authenc after.. */
ssi_aead_xcbc_setup_digest_desc(req, desc, seq_size);
- ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc, seq_size, direct);
+ ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc,
+ seq_size, direct);
ssi_aead_process_digest_result_desc(req, desc, seq_size);
- } else { /*DECRYPT*/
+ } else {
+ /*DECRYPT*/
/* authenc first.. */
ssi_aead_xcbc_setup_digest_desc(req, desc, seq_size);
- ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc, seq_size, direct);
- /* decrypt after..*/
+ ssi_aead_process_authenc_data_desc(req, DIN_HASH, desc,
+ seq_size, direct);
+ /* decrypt after.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
/* read the digest result with setting the completion bit
* must be after the cipher operation
@@ -1334,7 +1349,7 @@ static int validate_data_size(struct ssi_aead_ctx *ctx,
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
unsigned int assoclen = req->assoclen;
unsigned int cipherlen = (direct == DRV_CRYPTO_DIRECTION_DECRYPT) ?
- (req->cryptlen - ctx->authsize) : req->cryptlen;
+ (req->cryptlen - ctx->authsize) : req->cryptlen;
if (unlikely((direct == DRV_CRYPTO_DIRECTION_DECRYPT) &&
(req->cryptlen < ctx->authsize)))
@@ -1425,10 +1440,8 @@ static int set_msg_len(u8 *block, unsigned int msglen, unsigned int csize)
return 0;
}
-static inline int ssi_aead_ccm(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline int ssi_aead_ccm(struct aead_request *req,
+ struct cc_hw_desc desc[], unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -1507,7 +1520,8 @@ static inline int ssi_aead_ccm(
/* process the cipher */
if (req_ctx->cryptlen != 0)
- ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, &idx);
+ ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc,
+ &idx);
/* Read temporal MAC */
hw_desc_init(&desc[idx]);
@@ -1564,8 +1578,7 @@ static int config_ccm_adata(struct aead_request *req)
u8 *ctr_count_0 = req_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET;
unsigned int cryptlen = (req_ctx->gen_ctx.op_type ==
DRV_CRYPTO_DIRECTION_ENCRYPT) ?
- req->cryptlen :
- (req->cryptlen - ctx->authsize);
+ req->cryptlen : (req->cryptlen - ctx->authsize);
int rc;
memset(req_ctx->mac_buf, 0, AES_BLOCK_SIZE);
@@ -1589,7 +1602,7 @@ static int config_ccm_adata(struct aead_request *req)
rc = set_msg_len(b0 + 16 - l, cryptlen, l); /* Write L'. */
if (rc != 0)
return rc;
- /* END of "taken from crypto/ccm.c" */
+ /* END of "taken from crypto/ccm.c" */
/* l(a) - size of associated data. */
req_ctx->ccm_hdr_size = format_ccm_a0(a0, req->assoclen);
@@ -1614,8 +1627,10 @@ static void ssi_rfc4309_ccm_process(struct aead_request *req)
areq_ctx->ctr_iv[0] = 3; /* For RFC 4309, always use 4 bytes for message length (at most 2^32-1 bytes). */
/* In RFC 4309 there is an 11-bytes nonce+IV part, that we build here. */
- memcpy(areq_ctx->ctr_iv + CCM_BLOCK_NONCE_OFFSET, ctx->ctr_nonce, CCM_BLOCK_NONCE_SIZE);
- memcpy(areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET, req->iv, CCM_BLOCK_IV_SIZE);
+ memcpy(areq_ctx->ctr_iv + CCM_BLOCK_NONCE_OFFSET, ctx->ctr_nonce,
+ CCM_BLOCK_NONCE_SIZE);
+ memcpy(areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET, req->iv,
+ CCM_BLOCK_IV_SIZE);
req->iv = areq_ctx->ctr_iv;
req->assoclen -= CCM_BLOCK_IV_SIZE;
}
@@ -1623,10 +1638,9 @@ static void ssi_rfc4309_ccm_process(struct aead_request *req)
#if SSI_CC_HAS_AES_GCM
-static inline void ssi_aead_gcm_setup_ghash_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_gcm_setup_ghash_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -1701,10 +1715,9 @@ static inline void ssi_aead_gcm_setup_ghash_desc(
*seq_size = idx;
}
-static inline void ssi_aead_gcm_setup_gctr_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_gcm_setup_gctr_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -1739,10 +1752,9 @@ static inline void ssi_aead_gcm_setup_gctr_desc(
*seq_size = idx;
}
-static inline void ssi_aead_process_gcm_result_desc(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline void ssi_aead_process_gcm_result_desc(struct aead_request *req,
+ struct cc_hw_desc desc[],
+ unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -1805,10 +1817,8 @@ static inline void ssi_aead_process_gcm_result_desc(
*seq_size = idx;
}
-static inline int ssi_aead_gcm(
- struct aead_request *req,
- struct cc_hw_desc desc[],
- unsigned int *seq_size)
+static inline int ssi_aead_gcm(struct aead_request *req,
+ struct cc_hw_desc desc[], unsigned int *seq_size)
{
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
unsigned int idx = *seq_size;
@@ -1831,7 +1841,6 @@ static inline int ssi_aead_gcm(
idx = *seq_size;
return 0;
}
-
// for gcm and rfc4106.
ssi_aead_gcm_setup_ghash_desc(req, desc, seq_size);
/* process(ghash) assoc data */
@@ -1840,7 +1849,8 @@ static inline int ssi_aead_gcm(
ssi_aead_gcm_setup_gctr_desc(req, desc, seq_size);
/* process(gctr+ghash) */
if (req_ctx->cryptlen != 0)
- ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, seq_size);
+ ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc,
+ seq_size);
ssi_aead_process_gcm_result_desc(req, desc, seq_size);
idx = *seq_size;
@@ -1848,9 +1858,8 @@ static inline int ssi_aead_gcm(
}
#ifdef CC_DEBUG
-static inline void ssi_aead_dump_gcm(
- const char *title,
- struct aead_request *req)
+static inline void ssi_aead_dump_gcm(const char *title,
+ struct aead_request *req)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -1860,13 +1869,15 @@ static inline void ssi_aead_dump_gcm(
return;
if (title) {
- SSI_LOG_DEBUG("----------------------------------------------------------------------------------");
+ SSI_LOG_DEBUG
+ ("----------------------------------------------------------------------------------");
SSI_LOG_DEBUG("%s\n", title);
}
- SSI_LOG_DEBUG("cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d\n",
- ctx->cipher_mode, ctx->authsize, ctx->enc_keylen,
- req->assoclen, req_ctx->cryptlen);
+ SSI_LOG_DEBUG
+ ("cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d\n",
+ ctx->cipher_mode, ctx->authsize, ctx->enc_keylen, req->assoclen,
+ req_ctx->cryptlen);
if (ctx->enckey)
dump_byte_array("mac key", ctx->enckey, 16);
@@ -1881,13 +1892,16 @@ static inline void ssi_aead_dump_gcm(
dump_byte_array("mac_buf", req_ctx->mac_buf, AES_BLOCK_SIZE);
- dump_byte_array("gcm_len_block", req_ctx->gcm_len_block.len_a, AES_BLOCK_SIZE);
+ dump_byte_array("gcm_len_block", req_ctx->gcm_len_block.len_a,
+ AES_BLOCK_SIZE);
if (req->src && req->cryptlen)
- dump_byte_array("req->src", sg_virt(req->src), req->cryptlen + req->assoclen);
+ dump_byte_array("req->src", sg_virt(req->src),
+ req->cryptlen + req->assoclen);
if (req->dst)
- dump_byte_array("req->dst", sg_virt(req->dst), req->cryptlen + ctx->authsize + req->assoclen);
+ dump_byte_array("req->dst", sg_virt(req->dst),
+ req->cryptlen + ctx->authsize + req->assoclen);
}
#endif
@@ -1899,11 +1913,12 @@ static int config_gcm_context(struct aead_request *req)
unsigned int cryptlen = (req_ctx->gen_ctx.op_type ==
DRV_CRYPTO_DIRECTION_ENCRYPT) ?
- req->cryptlen :
- (req->cryptlen - ctx->authsize);
+ req->cryptlen : (req->cryptlen - ctx->authsize);
__be32 counter = cpu_to_be32(2);
- SSI_LOG_DEBUG("%s() cryptlen = %d, req->assoclen = %d ctx->authsize = %d\n", __func__, cryptlen, req->assoclen, ctx->authsize);
+ SSI_LOG_DEBUG
+ ("%s() cryptlen = %d, req->assoclen = %d ctx->authsize = %d\n",
+ __func__, cryptlen, req->assoclen, ctx->authsize);
memset(req_ctx->hkey, 0, AES_BLOCK_SIZE);
@@ -1926,7 +1941,9 @@ static int config_gcm_context(struct aead_request *req)
} else { //rfc4543=> all data(AAD,IV,Plain) are considered additional data that is nothing is encrypted.
__be64 temp64;
- temp64 = cpu_to_be64((req->assoclen + GCM_BLOCK_RFC4_IV_SIZE + cryptlen) * 8);
+ temp64 =
+ cpu_to_be64((req->assoclen + GCM_BLOCK_RFC4_IV_SIZE +
+ cryptlen) * 8);
memcpy(&req_ctx->gcm_len_block.len_a, &temp64, sizeof(temp64));
temp64 = 0;
memcpy(&req_ctx->gcm_len_block.len_c, &temp64, 8);
@@ -1941,15 +1958,18 @@ static void ssi_rfc4_gcm_process(struct aead_request *req)
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
- memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_NONCE_OFFSET, ctx->ctr_nonce, GCM_BLOCK_RFC4_NONCE_SIZE);
- memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_IV_OFFSET, req->iv, GCM_BLOCK_RFC4_IV_SIZE);
+ memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_NONCE_OFFSET, ctx->ctr_nonce,
+ GCM_BLOCK_RFC4_NONCE_SIZE);
+ memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_IV_OFFSET, req->iv,
+ GCM_BLOCK_RFC4_IV_SIZE);
req->iv = areq_ctx->ctr_iv;
req->assoclen -= GCM_BLOCK_RFC4_IV_SIZE;
}
#endif /*SSI_CC_HAS_AES_GCM*/
-static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction direct)
+static int ssi_aead_process(struct aead_request *req,
+ enum drv_crypto_direction direct)
{
int rc = 0;
int seq_len = 0;
@@ -1960,10 +1980,11 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
struct device *dev = &ctx->drvdata->plat_dev->dev;
struct ssi_crypto_req ssi_req = {};
- SSI_LOG_DEBUG("%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n",
- ((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"),
- ctx, req, req->iv, sg_virt(req->src), req->src->offset,
- sg_virt(req->dst), req->dst->offset, req->cryptlen);
+ SSI_LOG_DEBUG
+ ("%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n",
+ ((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"),
+ ctx, req, req->iv, sg_virt(req->src), req->src->offset,
+ sg_virt(req->dst), req->dst->offset, req->cryptlen);
/* STAT_PHASE_0: Init and sanity checks */
@@ -1990,13 +2011,14 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
/* Build CTR IV - Copy nonce from last 4 bytes in
* CTR key to first 4 bytes in CTR IV
*/
- memcpy(areq_ctx->ctr_iv, ctx->ctr_nonce, CTR_RFC3686_NONCE_SIZE);
+ memcpy(areq_ctx->ctr_iv, ctx->ctr_nonce,
+ CTR_RFC3686_NONCE_SIZE);
if (!areq_ctx->backup_giv) /*User none-generated IV*/
memcpy(areq_ctx->ctr_iv + CTR_RFC3686_NONCE_SIZE,
req->iv, CTR_RFC3686_IV_SIZE);
/* Initialize counter portion of counter block */
*(__be32 *)(areq_ctx->ctr_iv + CTR_RFC3686_NONCE_SIZE +
- CTR_RFC3686_IV_SIZE) = cpu_to_be32(1);
+ CTR_RFC3686_IV_SIZE) = cpu_to_be32(1);
/* Replace with counter iv */
req->iv = areq_ctx->ctr_iv;
@@ -2005,10 +2027,11 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
(ctx->cipher_mode == DRV_CIPHER_GCTR)) {
areq_ctx->hw_iv_size = AES_BLOCK_SIZE;
if (areq_ctx->ctr_iv != req->iv) {
- memcpy(areq_ctx->ctr_iv, req->iv, crypto_aead_ivsize(tfm));
+ memcpy(areq_ctx->ctr_iv, req->iv,
+ crypto_aead_ivsize(tfm));
req->iv = areq_ctx->ctr_iv;
}
- } else {
+ } else {
areq_ctx->hw_iv_size = crypto_aead_ivsize(tfm);
}
@@ -2016,7 +2039,9 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
if (ctx->cipher_mode == DRV_CIPHER_CCM) {
rc = config_ccm_adata(req);
if (unlikely(rc != 0)) {
- SSI_LOG_ERR("config_ccm_adata() returned with a failure %d!", rc);
+ SSI_LOG_ERR
+ ("config_ccm_adata() returned with a failure %d!",
+ rc);
goto exit;
}
} else {
@@ -2030,7 +2055,9 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
if (ctx->cipher_mode == DRV_CIPHER_GCTR) {
rc = config_gcm_context(req);
if (unlikely(rc != 0)) {
- SSI_LOG_ERR("config_gcm_context() returned with a failure %d!", rc);
+ SSI_LOG_ERR
+ ("config_gcm_context() returned with a failure %d!",
+ rc);
goto exit;
}
}
@@ -2046,7 +2073,9 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
if (areq_ctx->backup_giv) {
/* set the DMA mapped IV address*/
if (ctx->cipher_mode == DRV_CIPHER_CTR) {
- ssi_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr + CTR_RFC3686_NONCE_SIZE;
+ ssi_req.ivgen_dma_addr[0] =
+ areq_ctx->gen_ctx.iv_dma_addr +
+ CTR_RFC3686_NONCE_SIZE;
ssi_req.ivgen_dma_addr_len = 1;
} else if (ctx->cipher_mode == DRV_CIPHER_CCM) {
/* In ccm, the IV needs to exist both inside B0 and inside the counter.
@@ -2054,12 +2083,18 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
* it to the user).
* So, using 3 (identical) IV outputs.
*/
- ssi_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr + CCM_BLOCK_IV_OFFSET;
- ssi_req.ivgen_dma_addr[1] = sg_dma_address(&areq_ctx->ccm_adata_sg) + CCM_B0_OFFSET + CCM_BLOCK_IV_OFFSET;
- ssi_req.ivgen_dma_addr[2] = sg_dma_address(&areq_ctx->ccm_adata_sg) + CCM_CTR_COUNT_0_OFFSET + CCM_BLOCK_IV_OFFSET;
+ ssi_req.ivgen_dma_addr[0] =
+ areq_ctx->gen_ctx.iv_dma_addr + CCM_BLOCK_IV_OFFSET;
+ ssi_req.ivgen_dma_addr[1] =
+ sg_dma_address(&areq_ctx->ccm_adata_sg) +
+ CCM_B0_OFFSET + CCM_BLOCK_IV_OFFSET;
+ ssi_req.ivgen_dma_addr[2] =
+ sg_dma_address(&areq_ctx->ccm_adata_sg) +
+ CCM_CTR_COUNT_0_OFFSET + CCM_BLOCK_IV_OFFSET;
ssi_req.ivgen_dma_addr_len = 3;
} else {
- ssi_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr;
+ ssi_req.ivgen_dma_addr[0] =
+ areq_ctx->gen_ctx.iv_dma_addr;
ssi_req.ivgen_dma_addr_len = 1;
}
@@ -2091,7 +2126,7 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
if (ctx->cipher_mode == DRV_CIPHER_GCTR)
ssi_aead_gcm(req, desc, &seq_len);
#endif /*SSI_CC_HAS_AES_GCM*/
- break;
+ break;
#endif
default:
SSI_LOG_ERR("Unsupported authenc (%d)\n", ctx->auth_mode);
@@ -2210,7 +2245,8 @@ static int ssi_rfc4309_ccm_decrypt(struct aead_request *req)
#if SSI_CC_HAS_AES_GCM
-static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
+static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
+ unsigned int keylen)
{
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
int rc = 0;
@@ -2228,7 +2264,8 @@ static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsign
return rc;
}
-static int ssi_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
+static int ssi_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
+ unsigned int keylen)
{
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
int rc = 0;
@@ -2401,259 +2438,260 @@ static int ssi_rfc4543_gcm_decrypt(struct aead_request *req)
/* DX Block aead alg */
static struct ssi_alg_template aead_algs[] = {
{
- .name = "authenc(hmac(sha1),cbc(aes))",
- .driver_name = "authenc-hmac-sha1-cbc-aes-dx",
- .blocksize = AES_BLOCK_SIZE,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CBC,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_SHA1,
- },
+ .name = "authenc(hmac(sha1),cbc(aes))",
+ .driver_name = "authenc-hmac-sha1-cbc-aes-dx",
+ .blocksize = AES_BLOCK_SIZE,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CBC,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_SHA1,
+ },
{
- .name = "authenc(hmac(sha1),cbc(des3_ede))",
- .driver_name = "authenc-hmac-sha1-cbc-des3-dx",
- .blocksize = DES3_EDE_BLOCK_SIZE,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CBC,
- .flow_mode = S_DIN_to_DES,
- .auth_mode = DRV_HASH_SHA1,
- },
+ .name = "authenc(hmac(sha1),cbc(des3_ede))",
+ .driver_name = "authenc-hmac-sha1-cbc-des3-dx",
+ .blocksize = DES3_EDE_BLOCK_SIZE,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CBC,
+ .flow_mode = S_DIN_to_DES,
+ .auth_mode = DRV_HASH_SHA1,
+ },
{
- .name = "authenc(hmac(sha256),cbc(aes))",
- .driver_name = "authenc-hmac-sha256-cbc-aes-dx",
- .blocksize = AES_BLOCK_SIZE,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CBC,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_SHA256,
- },
+ .name = "authenc(hmac(sha256),cbc(aes))",
+ .driver_name = "authenc-hmac-sha256-cbc-aes-dx",
+ .blocksize = AES_BLOCK_SIZE,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CBC,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_SHA256,
+ },
{
- .name = "authenc(hmac(sha256),cbc(des3_ede))",
- .driver_name = "authenc-hmac-sha256-cbc-des3-dx",
- .blocksize = DES3_EDE_BLOCK_SIZE,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CBC,
- .flow_mode = S_DIN_to_DES,
- .auth_mode = DRV_HASH_SHA256,
- },
+ .name = "authenc(hmac(sha256),cbc(des3_ede))",
+ .driver_name = "authenc-hmac-sha256-cbc-des3-dx",
+ .blocksize = DES3_EDE_BLOCK_SIZE,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CBC,
+ .flow_mode = S_DIN_to_DES,
+ .auth_mode = DRV_HASH_SHA256,
+ },
{
- .name = "authenc(xcbc(aes),cbc(aes))",
- .driver_name = "authenc-xcbc-aes-cbc-aes-dx",
- .blocksize = AES_BLOCK_SIZE,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = AES_BLOCK_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CBC,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_XCBC_MAC,
- },
+ .name = "authenc(xcbc(aes),cbc(aes))",
+ .driver_name = "authenc-xcbc-aes-cbc-aes-dx",
+ .blocksize = AES_BLOCK_SIZE,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CBC,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_XCBC_MAC,
+ },
{
- .name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
- .driver_name = "authenc-hmac-sha1-rfc3686-ctr-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = CTR_RFC3686_IV_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CTR,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_SHA1,
- },
+ .name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
+ .driver_name = "authenc-hmac-sha1-rfc3686-ctr-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = CTR_RFC3686_IV_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CTR,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_SHA1,
+ },
{
- .name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
- .driver_name = "authenc-hmac-sha256-rfc3686-ctr-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = CTR_RFC3686_IV_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CTR,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_SHA256,
- },
+ .name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
+ .driver_name = "authenc-hmac-sha256-rfc3686-ctr-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = CTR_RFC3686_IV_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CTR,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_SHA256,
+ },
{
- .name = "authenc(xcbc(aes),rfc3686(ctr(aes)))",
- .driver_name = "authenc-xcbc-aes-rfc3686-ctr-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_aead_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = CTR_RFC3686_IV_SIZE,
- .maxauthsize = AES_BLOCK_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CTR,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_XCBC_MAC,
- },
+ .name = "authenc(xcbc(aes),rfc3686(ctr(aes)))",
+ .driver_name = "authenc-xcbc-aes-rfc3686-ctr-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_aead_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = CTR_RFC3686_IV_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CTR,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_XCBC_MAC,
+ },
#if SSI_CC_HAS_AES_CCM
{
- .name = "ccm(aes)",
- .driver_name = "ccm-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_ccm_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = AES_BLOCK_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CCM,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_NULL,
- },
+ .name = "ccm(aes)",
+ .driver_name = "ccm-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_ccm_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CCM,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_NULL,
+ },
{
- .name = "rfc4309(ccm(aes))",
- .driver_name = "rfc4309-ccm-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_rfc4309_ccm_setkey,
- .setauthsize = ssi_rfc4309_ccm_setauthsize,
- .encrypt = ssi_rfc4309_ccm_encrypt,
- .decrypt = ssi_rfc4309_ccm_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = CCM_BLOCK_IV_SIZE,
- .maxauthsize = AES_BLOCK_SIZE,
- },
- .cipher_mode = DRV_CIPHER_CCM,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_NULL,
- },
-#endif /*SSI_CC_HAS_AES_CCM*/
+ .name = "rfc4309(ccm(aes))",
+ .driver_name = "rfc4309-ccm-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_rfc4309_ccm_setkey,
+ .setauthsize = ssi_rfc4309_ccm_setauthsize,
+ .encrypt = ssi_rfc4309_ccm_encrypt,
+ .decrypt = ssi_rfc4309_ccm_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = CCM_BLOCK_IV_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_CCM,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_NULL,
+ },
+#endif /*SSI_CC_HAS_AES_CCM */
#if SSI_CC_HAS_AES_GCM
{
- .name = "gcm(aes)",
- .driver_name = "gcm-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_aead_setkey,
- .setauthsize = ssi_gcm_setauthsize,
- .encrypt = ssi_aead_encrypt,
- .decrypt = ssi_aead_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = 12,
- .maxauthsize = AES_BLOCK_SIZE,
- },
- .cipher_mode = DRV_CIPHER_GCTR,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_NULL,
- },
+ .name = "gcm(aes)",
+ .driver_name = "gcm-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_aead_setkey,
+ .setauthsize = ssi_gcm_setauthsize,
+ .encrypt = ssi_aead_encrypt,
+ .decrypt = ssi_aead_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = 12,
+ .maxauthsize = AES_BLOCK_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_GCTR,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_NULL,
+ },
{
- .name = "rfc4106(gcm(aes))",
- .driver_name = "rfc4106-gcm-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_rfc4106_gcm_setkey,
- .setauthsize = ssi_rfc4106_gcm_setauthsize,
- .encrypt = ssi_rfc4106_gcm_encrypt,
- .decrypt = ssi_rfc4106_gcm_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = GCM_BLOCK_RFC4_IV_SIZE,
- .maxauthsize = AES_BLOCK_SIZE,
- },
- .cipher_mode = DRV_CIPHER_GCTR,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_NULL,
- },
+ .name = "rfc4106(gcm(aes))",
+ .driver_name = "rfc4106-gcm-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_rfc4106_gcm_setkey,
+ .setauthsize = ssi_rfc4106_gcm_setauthsize,
+ .encrypt = ssi_rfc4106_gcm_encrypt,
+ .decrypt = ssi_rfc4106_gcm_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = GCM_BLOCK_RFC4_IV_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_GCTR,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_NULL,
+ },
{
- .name = "rfc4543(gcm(aes))",
- .driver_name = "rfc4543-gcm-aes-dx",
- .blocksize = 1,
- .type = CRYPTO_ALG_TYPE_AEAD,
- .template_aead = {
- .setkey = ssi_rfc4543_gcm_setkey,
- .setauthsize = ssi_rfc4543_gcm_setauthsize,
- .encrypt = ssi_rfc4543_gcm_encrypt,
- .decrypt = ssi_rfc4543_gcm_decrypt,
- .init = ssi_aead_init,
- .exit = ssi_aead_exit,
- .ivsize = GCM_BLOCK_RFC4_IV_SIZE,
- .maxauthsize = AES_BLOCK_SIZE,
- },
- .cipher_mode = DRV_CIPHER_GCTR,
- .flow_mode = S_DIN_to_AES,
- .auth_mode = DRV_HASH_NULL,
- },
-#endif /*SSI_CC_HAS_AES_GCM*/
+ .name = "rfc4543(gcm(aes))",
+ .driver_name = "rfc4543-gcm-aes-dx",
+ .blocksize = 1,
+ .type = CRYPTO_ALG_TYPE_AEAD,
+ .template_aead = {
+ .setkey = ssi_rfc4543_gcm_setkey,
+ .setauthsize = ssi_rfc4543_gcm_setauthsize,
+ .encrypt = ssi_rfc4543_gcm_encrypt,
+ .decrypt = ssi_rfc4543_gcm_decrypt,
+ .init = ssi_aead_init,
+ .exit = ssi_aead_exit,
+ .ivsize = GCM_BLOCK_RFC4_IV_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ },
+ .cipher_mode = DRV_CIPHER_GCTR,
+ .flow_mode = S_DIN_to_AES,
+ .auth_mode = DRV_HASH_NULL,
+ },
+#endif /*SSI_CC_HAS_AES_GCM */
};
-static struct ssi_crypto_alg *ssi_aead_create_alg(struct ssi_alg_template *template)
+static struct ssi_crypto_alg *ssi_aead_create_alg(struct ssi_alg_template
+ *template)
{
struct ssi_crypto_alg *t_alg;
struct aead_alg *alg;
@@ -2673,7 +2711,7 @@ static struct ssi_crypto_alg *ssi_aead_create_alg(struct ssi_alg_template *templ
alg->base.cra_ctxsize = sizeof(struct ssi_aead_ctx);
alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
- template->type;
+ template->type;
alg->init = ssi_aead_init;
alg->exit = ssi_aead_exit;
@@ -2690,11 +2728,12 @@ int ssi_aead_free(struct ssi_drvdata *drvdata)
{
struct ssi_crypto_alg *t_alg, *n;
struct ssi_aead_handle *aead_handle =
- (struct ssi_aead_handle *)drvdata->aead_handle;
+ (struct ssi_aead_handle *)drvdata->aead_handle;
if (aead_handle) {
/* Remove registered algs */
- list_for_each_entry_safe(t_alg, n, &aead_handle->aead_list, entry) {
+ list_for_each_entry_safe(t_alg, n, &aead_handle->aead_list,
+ entry) {
crypto_unregister_aead(&t_alg->aead_alg);
list_del(&t_alg->entry);
kfree(t_alg);
@@ -2722,8 +2761,8 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata)
INIT_LIST_HEAD(&aead_handle->aead_list);
drvdata->aead_handle = aead_handle;
- aead_handle->sram_workspace_addr = ssi_sram_mgr_alloc(
- drvdata, MAX_HMAC_DIGEST_SIZE);
+ aead_handle->sram_workspace_addr =
+ ssi_sram_mgr_alloc(drvdata, MAX_HMAC_DIGEST_SIZE);
if (aead_handle->sram_workspace_addr == NULL_SRAM_ADDR) {
SSI_LOG_ERR("SRAM pool exhausted\n");
rc = -ENOMEM;
@@ -2747,7 +2786,8 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata)
goto fail2;
} else {
list_add_tail(&t_alg->entry, &aead_handle->aead_list);
- SSI_LOG_DEBUG("Registered %s\n", t_alg->aead_alg.base.cra_driver_name);
+ SSI_LOG_DEBUG("Registered %s\n",
+ t_alg->aead_alg.base.cra_driver_name);
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 16/22] staging: ccree: fix spelling mistakes
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (14 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 15/22] staging: ccree: fix line indentation and breaks Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 17/22] staging: ccree: clean up comments Gilad Ben-Yossef
` (6 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Fix various spelling mistakes in comments.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_cipher.c | 2 +-
drivers/staging/ccree/ssi_hash.c | 2 +-
drivers/staging/ccree/ssi_hash.h | 2 +-
drivers/staging/ccree/ssi_ivgen.c | 2 +-
drivers/staging/ccree/ssi_request_mgr.c | 2 +-
drivers/staging/ccree/ssi_request_mgr.h | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index 8d65e97..e417bfd 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -697,7 +697,7 @@ static int ssi_blkcipher_complete(struct device *dev,
ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
- /*Set the inflight couter value to local variable*/
+ /*Set the inflight counter value to local variable*/
inflight_counter = ctx_p->drvdata->inflight_counter;
/*Decrease the inflight counter*/
if (ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 6baa449..cfd5f5c 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -2575,7 +2575,7 @@ static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx,
* \param drvdata
* \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256
*
- * \return u32 The address of the inital digest in SRAM
+ * \return u32 The address of the initial digest in SRAM
*/
ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode)
{
diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h
index 2400e38..c884727 100644
--- a/drivers/staging/ccree/ssi_hash.h
+++ b/drivers/staging/ccree/ssi_hash.h
@@ -95,7 +95,7 @@ ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode);
* \param drvdata
* \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
*
- * \return u32 The address of the inital digest in SRAM
+ * \return u32 The address of the initial digest in SRAM
*/
ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode);
diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c
index 93a2a94..ba70237 100644
--- a/drivers/staging/ccree/ssi_ivgen.c
+++ b/drivers/staging/ccree/ssi_ivgen.c
@@ -200,7 +200,7 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata)
}
ivgen_ctx = drvdata->ivgen_handle;
- /* Allocate pool's header for intial enc. key/IV */
+ /* Allocate pool's header for initial enc. key/IV */
ivgen_ctx->pool_meta = dma_alloc_coherent(device, SSI_IVPOOL_META_SIZE,
&ivgen_ctx->pool_meta_dma,
GFP_KERNEL);
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index 27324bb..9ca2536 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -205,7 +205,7 @@ static inline int request_mgr_queues_status_check(
unsigned long poll_queue;
/* SW queue is checked only once as it will not
- * be chaned during the poll becasue the spinlock_bh
+ * be chaned during the poll because the spinlock_bh
* is held by the thread
*/
if (unlikely(((req_mgr_h->req_queue_head + 1) &
diff --git a/drivers/staging/ccree/ssi_request_mgr.h b/drivers/staging/ccree/ssi_request_mgr.h
index bdbbf89..b248fb6 100644
--- a/drivers/staging/ccree/ssi_request_mgr.h
+++ b/drivers/staging/ccree/ssi_request_mgr.h
@@ -36,7 +36,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata);
* If "false": this function adds a dummy descriptor completion
* and waits upon completion signal.
*
- * \return int Returns -EINPROGRESS if "is_dout=ture"; "0" if "is_dout=false"
+ * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false"
*/
int send_request(
struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req,
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 17/22] staging: ccree: clean up comments
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (15 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 16/22] staging: ccree: fix spelling mistakes Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 18/22] staging: ccree: move over to BIT macro for bit defines Gilad Ben-Yossef
` (5 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Clean up comments: fix style, trim long lines and remove useless ones.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_aead.c | 40 +++++++++++++++++--------
drivers/staging/ccree/ssi_aead.h | 47 ++++++++++++++++++-----------
drivers/staging/ccree/ssi_buffer_mgr.c | 52 +++++++++++++++++++++------------
drivers/staging/ccree/ssi_cipher.c | 10 +++++--
drivers/staging/ccree/ssi_config.h | 7 +++--
drivers/staging/ccree/ssi_driver.c | 8 +++--
drivers/staging/ccree/ssi_driver.h | 9 ++++--
drivers/staging/ccree/ssi_hash.c | 16 +++++++---
drivers/staging/ccree/ssi_hash.h | 10 +++++--
drivers/staging/ccree/ssi_ivgen.c | 7 +++--
drivers/staging/ccree/ssi_ivgen.h | 3 +-
drivers/staging/ccree/ssi_request_mgr.c | 29 ++++++++++++------
drivers/staging/ccree/ssi_sysfs.c | 9 +++---
13 files changed, 167 insertions(+), 80 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 515a603..88305f0 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -267,7 +267,10 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req,
ctx->authsize,
SSI_SG_FROM_BUF);
- /* If an IV was generated, copy it back to the user provided buffer. */
+ /*
+ * If an IV was generated, copy it back to the user provided
+ * buffer.
+ */
if (areq_ctx->backup_giv) {
if (ctx->cipher_mode == DRV_CIPHER_CTR)
memcpy(areq_ctx->backup_giv,
@@ -288,8 +291,9 @@ static int xcbc_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx)
{
/* Load the AES key */
hw_desc_init(&desc[0]);
- /* We are using for the source/user key the same buffer as for the output keys,
- * because after this key loading it is not needed anymore
+ /* We are using for the source/user key the same buffer as for the
+ * output keys, because after this key loading it is not needed
+ * anymore.
*/
set_din_type(&desc[0], DMA_DLLI,
ctx->auth_state.xcbc.xcbc_keys_dma_addr, ctx->auth_keylen,
@@ -1570,7 +1574,9 @@ static int config_ccm_adata(struct aead_request *req)
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
//unsigned int size_of_a = 0, rem_a_size = 0;
unsigned int lp = req->iv[0];
- /* Note: The code assume that req->iv[0] already contains the value of L' of RFC3610 */
+ /* Note: The code assumes that req->iv[0] already contains the value
+ * of L' of RFC3610
+ */
unsigned int l = lp + 1; /* This is L' of RFC 3610. */
unsigned int m = ctx->authsize; /* This is M' of RFC 3610. */
u8 *b0 = req_ctx->ccm_config + CCM_B0_OFFSET;
@@ -1624,9 +1630,14 @@ static void ssi_rfc4309_ccm_process(struct aead_request *req)
/* L' */
memset(areq_ctx->ctr_iv, 0, AES_BLOCK_SIZE);
- areq_ctx->ctr_iv[0] = 3; /* For RFC 4309, always use 4 bytes for message length (at most 2^32-1 bytes). */
+ /* For RFC 4309, always use 4 bytes for message length
+ * (at most 2^32-1 bytes).
+ */
+ areq_ctx->ctr_iv[0] = 3;
- /* In RFC 4309 there is an 11-bytes nonce+IV part, that we build here. */
+ /* In RFC 4309 there is an 11-bytes nonce+IV part, that we build
+ * here.
+ */
memcpy(areq_ctx->ctr_iv + CCM_BLOCK_NONCE_OFFSET, ctx->ctr_nonce,
CCM_BLOCK_NONCE_SIZE);
memcpy(areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET, req->iv,
@@ -1701,7 +1712,9 @@ static inline void ssi_aead_gcm_setup_ghash_desc(struct aead_request *req,
set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
idx++;
- /* Load GHASH initial STATE (which is 0). (for any hash there is an initial state) */
+ /* Load GHASH initial STATE (which is 0). (for any hash there is an
+ * initial state).
+ */
hw_desc_init(&desc[idx]);
set_din_const(&desc[idx], 0x0, AES_BLOCK_SIZE);
set_dout_no_dma(&desc[idx], 0, 0, 1);
@@ -1938,7 +1951,10 @@ static int config_gcm_context(struct aead_request *req)
memcpy(&req_ctx->gcm_len_block.len_a, &temp64, sizeof(temp64));
temp64 = cpu_to_be64(cryptlen * 8);
memcpy(&req_ctx->gcm_len_block.len_c, &temp64, 8);
- } else { //rfc4543=> all data(AAD,IV,Plain) are considered additional data that is nothing is encrypted.
+ } else {
+ /* rfc4543=> all data(AAD,IV,Plain) are considered additional
+ * data that is nothing is encrypted.
+ */
__be64 temp64;
temp64 =
@@ -2078,10 +2094,10 @@ static int ssi_aead_process(struct aead_request *req,
CTR_RFC3686_NONCE_SIZE;
ssi_req.ivgen_dma_addr_len = 1;
} else if (ctx->cipher_mode == DRV_CIPHER_CCM) {
- /* In ccm, the IV needs to exist both inside B0 and inside the counter.
- * It is also copied to iv_dma_addr for other reasons (like returning
- * it to the user).
- * So, using 3 (identical) IV outputs.
+ /* In ccm, the IV needs to exist both inside B0 and
+ * inside the counter. It is also copied to
+ * iv_dma_addr for other reasons (like returning it
+ * to the user). So, using 3 (identical) IV outputs.
*/
ssi_req.ivgen_dma_addr[0] =
areq_ctx->gen_ctx.iv_dma_addr + CCM_BLOCK_IV_OFFSET;
diff --git a/drivers/staging/ccree/ssi_aead.h b/drivers/staging/ccree/ssi_aead.h
index e85bcd9..96586d8 100644
--- a/drivers/staging/ccree/ssi_aead.h
+++ b/drivers/staging/ccree/ssi_aead.h
@@ -58,13 +58,13 @@ enum aead_ccm_header_size {
struct aead_req_ctx {
/* Allocate cache line although only 4 bytes are needed to
- * assure next field falls @ cache line
- * Used for both: digest HW compare and CCM/GCM MAC value
+ * assure next field falls @ cache line
+ * Used for both: digest HW compare and CCM/GCM MAC value
*/
u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
- //used in gcm
+ /* used in gcm */
u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
@@ -74,22 +74,34 @@ struct aead_req_ctx {
} gcm_len_block;
u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
- unsigned int hw_iv_size ____cacheline_aligned; /*HW actual size input*/
- u8 backup_mac[MAX_MAC_SIZE]; /*used to prevent cache coherence problem*/
- u8 *backup_iv; /*store iv for generated IV flow*/
- u8 *backup_giv; /*store iv for rfc3686(ctr) flow*/
- dma_addr_t mac_buf_dma_addr; /* internal ICV DMA buffer */
- dma_addr_t ccm_iv0_dma_addr; /* buffer for internal ccm configurations */
- dma_addr_t icv_dma_addr; /* Phys. address of ICV */
+ /* HW actual size input */
+ unsigned int hw_iv_size ____cacheline_aligned;
+ /* used to prevent cache coherence problem */
+ u8 backup_mac[MAX_MAC_SIZE];
+ /* store iv for generated IV flow */
+ u8 *backup_iv;
+ /* store iv for rfc3686(ctr) flow */
+ u8 *backup_giv;
+ /* internal ICV DMA buffer */
+ dma_addr_t mac_buf_dma_addr;
+ /* buf for internal ccm configurations */
+ dma_addr_t ccm_iv0_dma_addr;
+ /* Phys. address of ICV */
+ dma_addr_t icv_dma_addr;
- //used in gcm
- dma_addr_t gcm_iv_inc1_dma_addr; /* buffer for internal gcm configurations */
- dma_addr_t gcm_iv_inc2_dma_addr; /* buffer for internal gcm configurations */
- dma_addr_t hkey_dma_addr; /* Phys. address of hkey */
- dma_addr_t gcm_block_len_dma_addr; /* Phys. address of gcm block len */
+ /* used in gcm */
+ /* buf for internal gcm configurations */
+ dma_addr_t gcm_iv_inc1_dma_addr;
+ /* buffer for internal gcm configurations */
+ dma_addr_t gcm_iv_inc2_dma_addr;
+ /* Phys. address of hkey */
+ dma_addr_t hkey_dma_addr;
+ /* Phys. address of gcm block len */
+ dma_addr_t gcm_block_len_dma_addr;
bool is_gcm4543;
- u8 *icv_virt_addr; /* Virt. address of ICV */
+ /* Virt. address of ICV */
+ u8 *icv_virt_addr;
struct async_gen_req_ctx gen_ctx;
struct ssi_mlli assoc;
struct ssi_mlli src;
@@ -108,7 +120,8 @@ struct aead_req_ctx {
enum drv_cipher_mode cipher_mode;
bool is_icv_fragmented;
bool is_single_pass;
- bool plaintext_authenticate_only; //for gcm_rfc4543
+ /* for gcm_rfc4543 */
+ bool plaintext_authenticate_only;
};
int ssi_aead_alloc(struct ssi_drvdata *drvdata);
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c
index 4be7b51..202387b 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -706,7 +706,8 @@ void ssi_buffer_mgr_unmap_aead_request(
size_to_skip += crypto_aead_ivsize(tfm);
/* copy mac to a temporary location to deal with possible
- * data memory overriding that caused by cache coherence problem.
+ * data memory overriding that caused by cache coherence
+ * problem.
*/
ssi_buffer_mgr_copy_scatterlist_portion(
areq_ctx->backup_mac, req->src,
@@ -742,10 +743,12 @@ static inline int ssi_buffer_mgr_get_aead_icv_nents(
icv_max_size = sgl->length;
if (last_entry_data_size > authsize) {
- nents = 0; /* ICV attached to data in last entry (not fragmented!) */
+ /* ICV attached to data in last entry (not fragmented!) */
+ nents = 0;
*is_icv_fragmented = false;
} else if (last_entry_data_size == authsize) {
- nents = 1; /* ICV placed in whole last entry (not fragmented!) */
+ /* ICV placed in whole last entry (not fragmented!) */
+ nents = 1;
*is_icv_fragmented = false;
} else if (icv_max_size > icv_required_size) {
nents = 1;
@@ -792,7 +795,8 @@ static inline int ssi_buffer_mgr_aead_chain_iv(
SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=%pad\n",
hw_iv_size, req->iv,
&areq_ctx->gen_ctx.iv_dma_addr);
- if (do_chain && areq_ctx->plaintext_authenticate_only) { // TODO: what about CTR?? ask Ron
+ if (do_chain && areq_ctx->plaintext_authenticate_only) {
+ /* TODO: what about CTR?? */
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
unsigned int iv_size_to_authenc = crypto_aead_ivsize(tfm);
unsigned int iv_ofs = GCM_BLOCK_RFC4_IV_OFFSET;
@@ -840,16 +844,22 @@ static inline int ssi_buffer_mgr_aead_chain_assoc(
goto chain_assoc_exit;
}
- //iterate over the sgl to see how many entries are for associated data
- //it is assumed that if we reach here , the sgl is already mapped
+ /* Iterate over the sgl to see how many entries are for associated
+ * data it is assumed that if we reach here , the sgl is already
+ * mapped
+ */
sg_index = current_sg->length;
- if (sg_index > size_of_assoc) { //the first entry in the scatter list contains all the associated data
+ if (sg_index > size_of_assoc) {
+ /* The first entry in the scatter list contains all the
+ * associated data
+ */
mapped_nents++;
} else {
while (sg_index <= size_of_assoc) {
current_sg = sg_next(current_sg);
- //if have reached the end of the sgl, then this is unexpected
- if (!current_sg) {
+ /* If have reached the end of the sgl, then this is
+ * unexpected
+ */ if (!current_sg) {
SSI_LOG_ERR("reached end of sg list. unexpected\n");
BUG();
}
@@ -971,8 +981,8 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
if (unlikely(areq_ctx->is_icv_fragmented)) {
/* Backup happens only when ICV is fragmented, ICV
- * verification is made by CPU compare in order to simplify
- * MAC verification upon request completion
+ * verification is made by CPU compare in order to
+ * simplify MAC verification upon request completion
*/
if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
if (!drvdata->coherent) {
@@ -1037,8 +1047,8 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
if (unlikely(areq_ctx->is_icv_fragmented)) {
/* Backup happens only when ICV is fragmented, ICV
- * verification is made by CPU compare in order to simplify
- * MAC verification upon request completion
+ * verification is made by CPU compare in order to
+ * simplify MAC verification upon request completion
*/
u32 size_to_skip = req->assoclen;
@@ -1119,7 +1129,8 @@ static inline int ssi_buffer_mgr_aead_chain_data(
int rc = 0;
u32 src_mapped_nents = 0, dst_mapped_nents = 0;
u32 offset = 0;
- unsigned int size_for_map = req->assoclen + req->cryptlen; /*non-inplace mode*/
+ /* Non-inplace mode */
+ unsigned int size_for_map = req->assoclen + req->cryptlen;
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
u32 sg_index = 0;
bool chained = false;
@@ -1305,8 +1316,9 @@ int ssi_buffer_mgr_map_aead_request(
if (is_gcm4543)
size_to_skip += crypto_aead_ivsize(tfm);
- /* copy mac to a temporary location to deal with possible
- * data memory overriding that caused by cache coherence problem.
+ /* Copy mac to a temporary location to deal with possible
+ * data memory overriding that caused by cache coherence
+ * problem.
*/
ssi_buffer_mgr_copy_scatterlist_portion(
areq_ctx->backup_mac, req->src,
@@ -1466,7 +1478,9 @@ int ssi_buffer_mgr_map_aead_request(
goto aead_map_failure;
}
- /* Mlli support -start building the MLLI according to the above results */
+ /* Mlli support - start building the MLLI according to the above
+ * results
+ */
if (unlikely(
(areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) ||
(areq_ctx->data_buff_type == SSI_DMA_BUF_MLLI))) {
@@ -1739,7 +1753,9 @@ void ssi_buffer_mgr_unmap_hash_request(
sg_dma_len(areq_ctx->buff_sg));
dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
if (!do_revert) {
- /* clean the previous data length for update operation */
+ /* Clean the previous data length for update
+ * operation
+ */
*prev_len = 0;
} else {
areq_ctx->buff_index ^= 1;
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index e417bfd..14930ce 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -310,10 +310,12 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
/* STAT_PHASE_0: Init and sanity checks */
#if SSI_CC_HAS_MULTI2
- /*last byte of key buffer is round number and should not be a part of key size*/
+ /* Last byte of key buffer is round number and should not be a part
+ * of key size
+ */
if (ctx_p->flow_mode == S_DIN_to_MULTI2)
keylen -= 1;
-#endif /*SSI_CC_HAS_MULTI2*/
+#endif /* SSI_CC_HAS_MULTI2 */
if (unlikely(validate_keys_sizes(ctx_p, keylen) != 0)) {
SSI_LOG_ERR("Unsupported key size %d.\n", keylen);
@@ -797,7 +799,9 @@ static int ssi_blkcipher_process(
rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, (!areq) ? 0 : 1);
if (areq) {
if (unlikely(rc != -EINPROGRESS)) {
- /* Failed to send the request or request completed synchronously */
+ /* Failed to send the request or request completed
+ * synchronously
+ */
ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
}
diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h
index ff7597c..b26812b 100644
--- a/drivers/staging/ccree/ssi_config.h
+++ b/drivers/staging/ccree/ssi_config.h
@@ -28,9 +28,12 @@
//#define DX_DUMP_DESCS
// #define DX_DUMP_BYTES
// #define CC_DEBUG
-#define ENABLE_CC_SYSFS /* Enable sysfs interface for debugging REE driver */
+
+/* Enable sysfs interface for debugging REE driver */
+#define ENABLE_CC_SYSFS
+
//#define DX_IRQ_DELAY 100000
-#define DMA_BIT_MASK_LEN 48 /* was 32 bit, but for juno's sake it was enlarged to 48 bit */
+#define DMA_BIT_MASK_LEN 48
#endif /*__DX_CONFIG_H__*/
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 0ce2f57..91c0b71 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -140,7 +140,9 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
drvdata->irq = irr;
/* Completion interrupt - most probable */
if (likely((irr & SSI_COMP_IRQ_MASK) != 0)) {
- /* Mask AXI completion interrupt - will be unmasked in Deferred service handler */
+ /* Mask AXI completion interrupt - will be unmasked in deferred
+ * service handler
+ */
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR),
imr | SSI_COMP_IRQ_MASK);
irr &= ~SSI_COMP_IRQ_MASK;
@@ -149,7 +151,9 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
#ifdef CC_SUPPORT_FIPS
/* TEE FIPS interrupt */
if (likely((irr & SSI_GPR0_IRQ_MASK) != 0)) {
- /* Mask interrupt - will be unmasked in Deferred service handler */
+ /* Mask interrupt - will be unmasked in deferred
+ * service handler
+ */
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR),
imr | SSI_GPR0_IRQ_MASK);
irr &= ~SSI_GPR0_IRQ_MASK;
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index 47c648a..e37a55a 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -115,9 +115,12 @@ struct ssi_crypto_req {
* generated IV would be placed in it by send_request().
* Same generated IV for all addresses!
*/
- unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */
- unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */
- struct completion seq_compl; /* request completion */
+ /* Amount of 'ivgen_dma_addr' elements to be filled. */
+ unsigned int ivgen_dma_addr_len;
+ /* The generated IV size required, 8/16 B allowed. */
+ unsigned int ivgen_size;
+ /* request completion */
+ struct completion seq_compl;
};
/**
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index cfd5f5c..04b5025 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -502,7 +502,9 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
ssi_req.user_arg = (void *)async_req;
}
- /* If HMAC then load hash IPAD xor key, if HASH then load initial digest */
+ /* If HMAC then load hash IPAD xor key, if HASH then load
+ * initial digest.
+ */
hw_desc_init(&desc[idx]);
set_cipher_mode(&desc[idx], ctx->hw_mode);
if (is_hmac) {
@@ -1193,7 +1195,9 @@ static int ssi_hash_setkey(void *hash,
set_flow_mode(&desc[idx], DIN_HASH);
idx++;
- /* Get the IPAD/OPAD xor key (Note, IPAD is the initial digest of the first HASH "update" state) */
+ /* Get the IPAD/OPAD xor key (Note, IPAD is the initial
+ * digest of the first HASH "update" state)
+ */
hw_desc_init(&desc[idx]);
set_cipher_mode(&desc[idx], ctx->hw_mode);
if (i > 0) /* Not first iteration */
@@ -1562,7 +1566,9 @@ static int ssi_mac_final(struct ahash_request *req)
set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
idx++;
- /* Initiate decryption of block state to previous block_state-XOR-M[n] */
+ /* Initiate decryption of block state to previous
+ * block_state-XOR-M[n]
+ */
hw_desc_init(&desc[idx]);
set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
CC_AES_BLOCK_SIZE, NS_BIT);
@@ -2269,7 +2275,9 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata)
larval_seq_len = 0;
#if (DX_DEV_SHA_MAX > 256)
- /* We are forced to swap each double-word larval before copying to sram */
+ /* We are forced to swap each double-word larval before
+ * copying to sram
+ */
for (i = 0; i < ARRAY_SIZE(sha384_init); i++) {
const u32 const0 = ((u32 *)((u64 *)&sha384_init[i]))[1];
const u32 const1 = ((u32 *)((u64 *)&sha384_init[i]))[0];
diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h
index c884727..8868cb1 100644
--- a/drivers/staging/ccree/ssi_hash.h
+++ b/drivers/staging/ccree/ssi_hash.h
@@ -41,7 +41,9 @@
#define CC_EXPORT_MAGIC 0xC2EE1070U
-// this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used for xcbc/cmac statesize
+/* This struct was taken from drivers/crypto/nx/nx-aes-xcbc.c
+ * and it is used for xcbc/cmac statesize
+ */
struct aeshash_state {
u8 state[AES_BLOCK_SIZE];
unsigned int count;
@@ -81,7 +83,8 @@ int ssi_hash_free(struct ssi_drvdata *drvdata);
* Gets the initial digest length
*
* \param drvdata
- * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
+ * \param mode The Hash mode. Supported modes:
+ * MD5 / SHA1 / SHA224 / SHA256 / SHA384 / SHA512
*
* \return u32 returns the address of the initial digest length in SRAM
*/
@@ -93,7 +96,8 @@ ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode);
* according to the given hash mode
*
* \param drvdata
- * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
+ * \param mode The Hash mode. Supported modes:
+ * MD5 / SHA1 / SHA224 / SHA256 / SHA384 / SHA512
*
* \return u32 The address of the initial digest in SRAM
*/
diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c
index ba70237..c14f165 100644
--- a/drivers/staging/ccree/ssi_ivgen.c
+++ b/drivers/staging/ccree/ssi_ivgen.c
@@ -230,7 +230,8 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata)
*
* \param drvdata Driver private context
* \param iv_out_dma Array of physical IV out addresses
- * \param iv_out_dma_len Length of iv_out_dma array (additional elements of iv_out_dma array are ignore)
+ * \param iv_out_dma_len Length of iv_out_dma array
+ * (additional elements of iv_out_dma array are ignored)
* \param iv_out_size May be 8 or 16 bytes long
* \param iv_seq IN/OUT array to the descriptors sequence
* \param iv_seq_len IN/OUT pointer to the sequence length
@@ -258,7 +259,9 @@ int ssi_ivgen_getiv(
return -EINVAL;
}
- //check that number of generated IV is limited to max dma address iv buffer size
+ /* Check that number of generated IV is limited to max dma address
+ * iv buffer size
+ */
if (iv_out_dma_len > SSI_MAX_IVGEN_DMA_ADDRESSES) {
/* The sequence will be longer than allowed */
return -EINVAL;
diff --git a/drivers/staging/ccree/ssi_ivgen.h b/drivers/staging/ccree/ssi_ivgen.h
index 961aea4..36f295d 100644
--- a/drivers/staging/ccree/ssi_ivgen.h
+++ b/drivers/staging/ccree/ssi_ivgen.h
@@ -53,7 +53,8 @@ int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata);
*
* \param drvdata Driver private context
* \param iv_out_dma Array of physical IV out addresses
- * \param iv_out_dma_len Length of iv_out_dma array (additional elements of iv_out_dma array are ignore)
+ * \param iv_out_dma_len Length of iv_out_dma array
+ * (additional elements of iv_out_dma array are ignored)
* \param iv_out_size May be 8 or 16 bytes long
* \param iv_seq IN/OUT array to the descriptors sequence
* \param iv_seq_len IN/OUT pointer to the sequence length
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index 9ca2536..b671eff 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -405,7 +405,9 @@ int send_request_init(
unsigned int total_seq_len = len; /*initial sequence length*/
int rc = 0;
- /* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */
+ /* Wait for space in HW and SW FIFO. Poll for as much as
+ * FIFO_TIMEOUT.
+ */
rc = request_mgr_queues_status_check(req_mgr_h, cc_base, total_seq_len);
if (unlikely(rc != 0))
return rc;
@@ -514,10 +516,14 @@ static void comp_handler(unsigned long devarg)
irq = (drvdata->irq & SSI_COMP_IRQ_MASK);
if (irq & SSI_COMP_IRQ_MASK) {
- /* To avoid the interrupt from firing as we unmask it, we clear it now */
+ /* To avoid the interrupt from firing as we unmask it,
+ * we clear it now
+ */
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK);
- /* Avoid race with above clear: Test completion counter once more */
+ /* Avoid race with above clear: Test completion counter
+ * once more
+ */
request_mgr_handle->axi_completed +=
cc_axi_comp_count(cc_base);
@@ -531,22 +537,27 @@ static void comp_handler(unsigned long devarg)
cc_axi_comp_count(cc_base);
} while (request_mgr_handle->axi_completed > 0);
- /* To avoid the interrupt from firing as we unmask it, we clear it now */
+ /* To avoid the interrupt from firing as we unmask it,
+ * we clear it now
+ */
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK);
- /* Avoid race with above clear: Test completion counter once more */
+ /* Avoid race with above clear: Test completion counter
+ * once more
+ */
request_mgr_handle->axi_completed +=
cc_axi_comp_count(cc_base);
}
}
- /* after verifing that there is nothing to do, Unmask AXI completion interrupt */
+ /* After verifing that there is nothing to do, Unmask AXI completion
+ * interrupt
+ */
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR),
CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR)) & ~irq);
}
-/*
- * resume the queue configuration - no need to take the lock as this happens inside
- * the spin lock protection
+/* Resume the queue configuration - no need to take the lock as this happens
+ * inside the spin lock protection
*/
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata)
diff --git a/drivers/staging/ccree/ssi_sysfs.c b/drivers/staging/ccree/ssi_sysfs.c
index 0655658..a0ab3c6 100644
--- a/drivers/staging/ccree/ssi_sysfs.c
+++ b/drivers/staging/ccree/ssi_sysfs.c
@@ -185,7 +185,7 @@ static ssize_t ssi_sys_stat_host_db_show(struct kobject *kobj,
buf_len = scnprintf(buf, PAGE_SIZE,
"phase\t\t\t\t\t\t\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n");
- if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
+ if (buf_len < 0)
return buf_len;
for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) {
for (j = 0; j < MAX_STAT_PHASES - 1; j++) {
@@ -203,7 +203,8 @@ static ssize_t ssi_sys_stat_host_db_show(struct kobject *kobj,
stat_name_db[i].stat_phase_name[j],
min_cyc, (unsigned int)avg, max_cyc,
stat_host_db[i][j].count);
- if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
+
+ if (tmp_len < 0)
return buf_len;
if (buf_len + tmp_len >= PAGE_SIZE)
return buf_len;
@@ -225,7 +226,7 @@ static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj,
buf_len = scnprintf(buf, PAGE_SIZE,
"phase\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n");
- if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
+ if (buf_len < 0)
return buf_len;
for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) {
if (stat_cc_db[i][STAT_PHASE_6].count > 0) {
@@ -241,7 +242,7 @@ static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj,
(unsigned int)avg, max_cyc,
stat_cc_db[i][STAT_PHASE_6].count);
- if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
+ if (tmp_len < 0)
return buf_len;
if (buf_len + tmp_len >= PAGE_SIZE)
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 18/22] staging: ccree: move over to BIT macro for bit defines
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (16 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 17/22] staging: ccree: clean up comments Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 19/22] staging: ccree: fix code indent Gilad Ben-Yossef
` (4 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Use BIT macro for bit definitions where needed.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_cipher.h | 10 +++++-----
drivers/staging/ccree/ssi_driver.c | 3 ++-
drivers/staging/ccree/ssi_driver.h | 6 +++---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/ccree/ssi_cipher.h b/drivers/staging/ccree/ssi_cipher.h
index 296b375..c9a83df 100644
--- a/drivers/staging/ccree/ssi_cipher.h
+++ b/drivers/staging/ccree/ssi_cipher.h
@@ -27,11 +27,11 @@
#include "ssi_buffer_mgr.h"
/* Crypto cipher flags */
-#define CC_CRYPTO_CIPHER_KEY_KFDE0 (1 << 0)
-#define CC_CRYPTO_CIPHER_KEY_KFDE1 (1 << 1)
-#define CC_CRYPTO_CIPHER_KEY_KFDE2 (1 << 2)
-#define CC_CRYPTO_CIPHER_KEY_KFDE3 (1 << 3)
-#define CC_CRYPTO_CIPHER_DU_SIZE_512B (1 << 4)
+#define CC_CRYPTO_CIPHER_KEY_KFDE0 BIT(0)
+#define CC_CRYPTO_CIPHER_KEY_KFDE1 BIT(1)
+#define CC_CRYPTO_CIPHER_KEY_KFDE2 BIT(2)
+#define CC_CRYPTO_CIPHER_KEY_KFDE3 BIT(3)
+#define CC_CRYPTO_CIPHER_DU_SIZE_512B BIT(4)
#define CC_CRYPTO_CIPHER_KEY_KFDE_MASK (CC_CRYPTO_CIPHER_KEY_KFDE0 | CC_CRYPTO_CIPHER_KEY_KFDE1 | CC_CRYPTO_CIPHER_KEY_KFDE2 | CC_CRYPTO_CIPHER_KEY_KFDE3)
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index 91c0b71..6ec5287 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -202,7 +202,8 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), val);
/* Unmask relevant interrupt cause */
- val = (~(SSI_COMP_IRQ_MASK | SSI_AXI_ERR_IRQ_MASK | SSI_GPR0_IRQ_MASK));
+ val = (unsigned int)(~(SSI_COMP_IRQ_MASK | SSI_AXI_ERR_IRQ_MASK |
+ SSI_GPR0_IRQ_MASK));
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), val);
#ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index e37a55a..0b9c7e6 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -68,12 +68,12 @@
#define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
(1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT))
-#define SSI_AXI_ERR_IRQ_MASK (1 << DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
+#define SSI_AXI_ERR_IRQ_MASK BIT(DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
-#define SSI_COMP_IRQ_MASK (1 << DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
+#define SSI_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
/* TEE FIPS status interrupt */
-#define SSI_GPR0_IRQ_MASK (1 << DX_HOST_IRR_GPR0_BIT_SHIFT)
+#define SSI_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT)
#define SSI_CRA_PRIO 3000
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 19/22] staging: ccree: fix code indent
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (17 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 18/22] staging: ccree: move over to BIT macro for bit defines Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 20/22] staging: ccree: replace noop macro with inline Gilad Ben-Yossef
` (3 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Fix multiple code indentation issues.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_buffer_mgr.c | 23 ++++++++++++-----------
drivers/staging/ccree/ssi_cipher.c | 2 +-
drivers/staging/ccree/ssi_sysfs.c | 4 +++-
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c
index 202387b..051d948 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -420,8 +420,8 @@ ssi_aead_handle_config_buf(struct device *dev,
sg_init_one(&areq_ctx->ccm_adata_sg, config_data, AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size);
if (unlikely(dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1,
DMA_TO_DEVICE) != 1)) {
- SSI_LOG_ERR("dma_map_sg() config buffer failed\n");
- return -ENOMEM;
+ SSI_LOG_ERR("dma_map_sg() config buffer failed\n");
+ return -ENOMEM;
}
SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad page=%p addr=%pK "
"offset=%u length=%u\n",
@@ -451,8 +451,8 @@ static inline int ssi_ahash_handle_curr_buf(struct device *dev,
sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt);
if (unlikely(dma_map_sg(dev, areq_ctx->buff_sg, 1,
DMA_TO_DEVICE) != 1)) {
- SSI_LOG_ERR("dma_map_sg() src buffer failed\n");
- return -ENOMEM;
+ SSI_LOG_ERR("dma_map_sg() src buffer failed\n");
+ return -ENOMEM;
}
SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad page=%p addr=%pK "
"offset=%u length=%u\n",
@@ -1050,15 +1050,16 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
* verification is made by CPU compare in order to
* simplify MAC verification upon request completion
*/
- u32 size_to_skip = req->assoclen;
+ u32 size_to_skip = req->assoclen;
- if (areq_ctx->is_gcm4543)
- size_to_skip += crypto_aead_ivsize(tfm);
+ if (areq_ctx->is_gcm4543)
+ size_to_skip += crypto_aead_ivsize(tfm);
- ssi_buffer_mgr_copy_scatterlist_portion(
- areq_ctx->backup_mac, req->src,
- size_to_skip + req->cryptlen - areq_ctx->req_authsize,
- size_to_skip + req->cryptlen, SSI_SG_TO_BUF);
+ ssi_buffer_mgr_copy_scatterlist_portion(areq_ctx->backup_mac,
+ req->src,
+ size_to_skip + req->cryptlen - areq_ctx->req_authsize,
+ size_to_skip + req->cryptlen,
+ SSI_SG_TO_BUF);
areq_ctx->icv_virt_addr = areq_ctx->backup_mac;
} else { /* Contig. ICV */
/*Should hanlde if the sg is not contig.*/
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index 14930ce..aa722e1 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -139,7 +139,7 @@ static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int siz
break;
case S_DIN_to_DES:
if (likely(IS_ALIGNED(size, DES_BLOCK_SIZE)))
- return 0;
+ return 0;
break;
#if SSI_CC_HAS_MULTI2
case S_DIN_to_MULTI2:
diff --git a/drivers/staging/ccree/ssi_sysfs.c b/drivers/staging/ccree/ssi_sysfs.c
index a0ab3c6..40cd3be2 100644
--- a/drivers/staging/ccree/ssi_sysfs.c
+++ b/drivers/staging/ccree/ssi_sysfs.c
@@ -316,7 +316,9 @@ static ssize_t ssi_sys_help_show(struct kobject *kobj,
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "Usage:\n");
for (i = 0; i < ARRAY_SIZE(help_str); i += 2)
- offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s\t\t%s\n", help_str[i], help_str[i + 1]);
+ offset += scnprintf(buf + offset, PAGE_SIZE - offset,
+ "%s\t\t%s\n", help_str[i],
+ help_str[i + 1]);
return offset;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 20/22] staging: ccree: replace noop macro with inline
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (18 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 19/22] staging: ccree: fix code indent Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 21/22] staging: ccree: save ciphertext for CTS IV Gilad Ben-Yossef
` (2 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Replace noop macro with a noop inline function
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_driver.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index 0b9c7e6..063a1cc 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -190,8 +190,8 @@ struct async_gen_req_ctx {
#ifdef DX_DUMP_BYTES
void dump_byte_array(const char *name, const u8 *the_array, unsigned long size);
#else
-#define dump_byte_array(name, array, size) do { \
-} while (0);
+static inline void dump_byte_array(const char *name, const u8 *the_array,
+ unsigned long size) {};
#endif
int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe);
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 21/22] staging: ccree: save ciphertext for CTS IV
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (19 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 20/22] staging: ccree: replace noop macro with inline Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-15 6:26 ` [PATCH v3 22/22] staging: ccree: remove BUG macro usage Gilad Ben-Yossef
2017-08-16 22:12 ` [PATCH v3 00/22] staging: ccree: fixes and simplifications Greg Kroah-Hartman
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
The crypto API requires saving the last blocks of ciphertext
in req->info for use as IV for CTS mode. The ccree driver
was not doing it and so failing tcrypt tests in some
situations. This patch fixes the issue.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_cipher.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index aa722e1..cc550b5 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -24,6 +24,7 @@
#include <crypto/ctr.h>
#include <crypto/des.h>
#include <crypto/xts.h>
+#include <crypto/scatterwalk.h>
#include "ssi_config.h"
#include "ssi_driver.h"
@@ -696,6 +697,7 @@ static int ssi_blkcipher_complete(struct device *dev,
{
int completion_error = 0;
u32 inflight_counter;
+ struct ablkcipher_request *req = (struct ablkcipher_request *)areq;
ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
@@ -706,6 +708,22 @@ static int ssi_blkcipher_complete(struct device *dev,
ctx_p->drvdata->inflight_counter--;
if (areq) {
+ /*
+ * The crypto API expects us to set the req->info to the last
+ * ciphertext block. For encrypt, simply copy from the result.
+ * For decrypt, we must copy from a saved buffer since this
+ * could be an in-place decryption operation and the src is
+ * lost by this point.
+ */
+ if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
+ memcpy(req->info, req_ctx->backup_info, ivsize);
+ kfree(req_ctx->backup_info);
+ } else {
+ scatterwalk_map_and_copy(req->info, req->dst,
+ (req->nbytes - ivsize),
+ ivsize, 0);
+ }
+
ablkcipher_request_complete(areq, completion_error);
return 0;
}
@@ -859,7 +877,6 @@ static int ssi_ablkcipher_encrypt(struct ablkcipher_request *req)
struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req);
unsigned int ivsize = crypto_ablkcipher_ivsize(ablk_tfm);
- req_ctx->backup_info = req->info;
req_ctx->is_giv = false;
return ssi_blkcipher_process(tfm, req_ctx, req->dst, req->src, req->nbytes, req->info, ivsize, (void *)req, DRV_CRYPTO_DIRECTION_ENCRYPT);
@@ -872,8 +889,18 @@ static int ssi_ablkcipher_decrypt(struct ablkcipher_request *req)
struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req);
unsigned int ivsize = crypto_ablkcipher_ivsize(ablk_tfm);
- req_ctx->backup_info = req->info;
+ /*
+ * Allocate and save the last IV sized bytes of the source, which will
+ * be lost in case of in-place decryption and might be needed for CTS.
+ */
+ req_ctx->backup_info = kmalloc(ivsize, GFP_KERNEL);
+ if (!req_ctx->backup_info)
+ return -ENOMEM;
+
+ scatterwalk_map_and_copy(req_ctx->backup_info, req->src,
+ (req->nbytes - ivsize), ivsize, 0);
req_ctx->is_giv = false;
+
return ssi_blkcipher_process(tfm, req_ctx, req->dst, req->src, req->nbytes, req->info, ivsize, (void *)req, DRV_CRYPTO_DIRECTION_DECRYPT);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 22/22] staging: ccree: remove BUG macro usage
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (20 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 21/22] staging: ccree: save ciphertext for CTS IV Gilad Ben-Yossef
@ 2017-08-15 6:26 ` Gilad Ben-Yossef
2017-08-16 22:12 ` [PATCH v3 00/22] staging: ccree: fixes and simplifications Greg Kroah-Hartman
22 siblings, 0 replies; 26+ messages in thread
From: Gilad Ben-Yossef @ 2017-08-15 6:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-crypto, driverdev-devel, devel,
linux-kernel
Cc: Ofir Drang
Replace BUG() macro usage that crash the kernel with alternatives
that signal error and/or try to recover.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_buffer_mgr.c | 14 ++++++--------
drivers/staging/ccree/ssi_cipher.c | 1 -
drivers/staging/ccree/ssi_pm.c | 3 ++-
drivers/staging/ccree/ssi_request_mgr.c | 23 +++++++++++++++++------
4 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c
index 051d948..6d5af50 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -86,11 +86,6 @@ static unsigned int ssi_buffer_mgr_get_sgl_nents(
unsigned int nents = 0;
while (nbytes != 0) {
- if (sg_is_chain(sg_list)) {
- SSI_LOG_ERR("Unexpected chained entry in sg (entry =0x%X)\n",
- nents);
- BUG();
- }
if (sg_list->length != 0) {
nents++;
/* get the number of bytes in the last entry */
@@ -861,7 +856,8 @@ static inline int ssi_buffer_mgr_aead_chain_assoc(
* unexpected
*/ if (!current_sg) {
SSI_LOG_ERR("reached end of sg list. unexpected\n");
- BUG();
+ rc = -EINVAL;
+ goto chain_assoc_exit;
}
sg_index += current_sg->length;
mapped_nents++;
@@ -1163,7 +1159,8 @@ static inline int ssi_buffer_mgr_aead_chain_data(
//if have reached the end of the sgl, then this is unexpected
if (!areq_ctx->src_sgl) {
SSI_LOG_ERR("reached end of sg list. unexpected\n");
- BUG();
+ return -EINVAL;
+ goto chain_data_exit;
}
sg_index += areq_ctx->src_sgl->length;
src_mapped_nents--;
@@ -1207,7 +1204,8 @@ static inline int ssi_buffer_mgr_aead_chain_data(
//if have reached the end of the sgl, then this is unexpected
if (!areq_ctx->dst_sgl) {
SSI_LOG_ERR("reached end of sg list. unexpected\n");
- BUG();
+ rc = -EINVAL;
+ goto chain_data_exit;
}
sg_index += areq_ctx->dst_sgl->length;
dst_mapped_nents--;
diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c
index cc550b5..73ba4eb 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -543,7 +543,6 @@ ssi_blkcipher_create_setup_desc(
break;
default:
SSI_LOG_ERR("Unsupported cipher mode (%d)\n", cipher_mode);
- BUG();
}
}
diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c
index 31325e6..a50671a 100644
--- a/drivers/staging/ccree/ssi_pm.c
+++ b/drivers/staging/ccree/ssi_pm.c
@@ -109,7 +109,8 @@ int ssi_power_mgr_runtime_put_suspend(struct device *dev)
rc = pm_runtime_put_autosuspend(dev);
} else {
/* Something wrong happens*/
- BUG();
+ SSI_LOG_ERR("request to suspend already suspended queue");
+ rc = -EBUSY;
}
return rc;
}
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index b671eff..8bf72e7 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -366,11 +366,16 @@ int send_request(
enqueue_seq(cc_base, &req_mgr_h->compl_desc, (is_dout ? 0 : 1));
if (unlikely(req_mgr_h->q_free_slots < total_seq_len)) {
- /*This means that there was a problem with the resume*/
- BUG();
+ /* This situation should never occur. Maybe indicating problem
+ * with resuming power. Set the free slot count to 0 and hope
+ * for the best.
+ */
+ SSI_LOG_ERR("HW free slot count mismatch.");
+ req_mgr_h->q_free_slots = 0;
+ } else {
+ /* Update the free slots in HW queue */
+ req_mgr_h->q_free_slots -= total_seq_len;
}
- /* Update the free slots in HW queue */
- req_mgr_h->q_free_slots -= total_seq_len;
spin_unlock_bh(&req_mgr_h->hw_lock);
@@ -459,8 +464,13 @@ static void proc_completions(struct ssi_drvdata *drvdata)
/* Dequeue request */
if (unlikely(request_mgr_handle->req_queue_head == request_mgr_handle->req_queue_tail)) {
- SSI_LOG_ERR("Request queue is empty req_queue_head==req_queue_tail==%u\n", request_mgr_handle->req_queue_head);
- BUG();
+ /* We are supposed to handle a completion but our
+ * queue is empty. This is not normal. Return and
+ * hope for the best.
+ */
+ SSI_LOG_ERR("Request queue is empty head == tail %u\n",
+ request_mgr_handle->req_queue_head);
+ goto out;
}
ssi_req = &request_mgr_handle->req_queue[request_mgr_handle->req_queue_tail];
@@ -486,6 +496,7 @@ static void proc_completions(struct ssi_drvdata *drvdata)
request_mgr_handle->req_queue_tail = (request_mgr_handle->req_queue_tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1);
SSI_LOG_DEBUG("Dequeue request tail=%u\n", request_mgr_handle->req_queue_tail);
SSI_LOG_DEBUG("Request completed. axi_completed=%d\n", request_mgr_handle->axi_completed);
+out:
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
rc = ssi_power_mgr_runtime_put_suspend(&plat_dev->dev);
if (rc != 0)
--
2.1.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v3 00/22] staging: ccree: fixes and simplifications
2017-08-15 6:26 [PATCH v3 00/22] staging: ccree: fixes and simplifications Gilad Ben-Yossef
` (21 preceding siblings ...)
2017-08-15 6:26 ` [PATCH v3 22/22] staging: ccree: remove BUG macro usage Gilad Ben-Yossef
@ 2017-08-16 22:12 ` Greg Kroah-Hartman
22 siblings, 0 replies; 26+ messages in thread
From: Greg Kroah-Hartman @ 2017-08-16 22:12 UTC (permalink / raw)
To: Gilad Ben-Yossef
Cc: linux-crypto, driverdev-devel, devel, linux-kernel, Ofir Drang
On Tue, Aug 15, 2017 at 09:26:28AM +0300, Gilad Ben-Yossef wrote:
> The series includes various bug fixes, code simplification and style
> cleanups.
>
> Changer from v2:
> - Drop M32R as supported architecture, which resolve the kbuild bot
> warnings on Joe Perches patch.
> - Bug fix that properly saves last bytes of ciphertext for CTS in
> skcipher
> - Even more coding style fixes
This patch series didn't apply at all, please fix up and resend.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 26+ messages in thread