From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752488AbdIMPO6 (ORCPT ); Wed, 13 Sep 2017 11:14:58 -0400 Received: from smtprelay2.synopsys.com ([198.182.60.111]:46359 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751882AbdIMPOu (ORCPT ); Wed, 13 Sep 2017 11:14:50 -0400 From: Eugeniy Paltsev To: Vineet Gupta , "linux-snps-arc@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , "Alexey Brodkin" , "robh+dt@kernel.org" , "devicetree@vger.kernel.org" Subject: Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency Thread-Topic: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency Thread-Index: AQHTK/PecVhJ+i4KvUWRAQRulGl0NKKxczGAgAFZbwA= Date: Wed, 13 Sep 2017 15:14:45 +0000 Message-ID: <1505315684.30546.32.camel@synopsys.com> References: <20170912182045.20941-1-Eugeniy.Paltsev@synopsys.com> <4df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com> In-Reply-To: <4df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.121.8.106] Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v8DFF4pU006421 On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote: > On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote: > > DW sdio controller has external ciu clock divider controlled > > via register in SDIO IP. It divides sdio_ref_clk > > (which comes from CGU) by 16 for default. So default mmcclk > > clock (which comes to sdk_in) is 25000000 Hz. > > > > So fix wrong current value (50000000 Hz) to actual 25000000 Hz. > > Is this a preventive fix or there are known issues with what we have today. Yes, it's kinda a preventive fix. We check axs10x ciu frequency when we found what hsdk ciu frequency was wrong and found that it is wring too. I tried to run SD stress test with wrong ciu frequency (50000000 Hz) and it passed successfully, but we must take into account the fact that it depends on SD card itself. For example: this SD card mostly works fine on HSDK with ciu  frequency 8x times higher than expected! Alexey says that he faced with unstable SD card work on axs103 earlier but he didn't save any artifacts about it. > Is this triggered after addition of AXS clk driver ? No. > > > > Signed-off-by: Eugeniy Paltsev > > --- > >   arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++- > >   1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi > > index 0ff7e07..7bdf581 100644 > > --- a/arch/arc/boot/dts/axs10x_mb.dtsi > > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi > > @@ -44,7 +44,14 @@ > >    > >    mmcclk: mmcclk { > >    compatible = "fixed-clock"; > > - clock-frequency = <50000000>; > > + /* > > +  * DW sdio controller has external ciu clock divider > > +  * controlled via register in SDIO IP. It divides > > +  * sdio_ref_clk (which comes from CGU) by 16 for > > +  * default. So default mmcclk clock (which comes > > +  * to sdk_in) is 25000000 Hz. > > +  */ > > + clock-frequency = <25000000>; > >    #clock-cells = <0>; > >    }; > >    > > --  Eugeniy Paltsev