From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755652AbdKGHod (ORCPT ); Tue, 7 Nov 2017 02:44:33 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:50844 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754872AbdKGHoa (ORCPT ); Tue, 7 Nov 2017 02:44:30 -0500 X-Google-Smtp-Source: ABhQp+QB1uap+TtI9BOsHPK7M3GZ7p1qElMY3ZFZaO6junbQw6nsUyvWqMx9/DaF4xy/T8w+0z5TdQ== From: Rick Chen To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, rick@andestech.com Cc: Rick Chen , Greentime Hu Subject: [PATCH v3 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer Date: Tue, 7 Nov 2017 15:19:51 +0800 Message-Id: <1510039193-32522-2-git-send-email-rickchen36@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1510039193-32522-1-git-send-email-rickchen36@gmail.com> References: <1510039193-32522-1-git-send-email-rickchen36@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set 32-bit timer0 as clock source and count downwards until underflow and restart again. It also set 32-bit timer1 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically. Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- drivers/clocksource/timer-atcpit100.c | 199 ++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 drivers/clocksource/timer-atcpit100.c diff --git a/drivers/clocksource/timer-atcpit100.c b/drivers/clocksource/timer-atcpit100.c new file mode 100644 index 0000000..1a5538b --- /dev/null +++ b/drivers/clocksource/timer-atcpit100.c @@ -0,0 +1,199 @@ +/* + * Andestech ATCPIT100 Timer Device Driver Implementation + * + * Copyright (C) 2016 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __iomem *base; +static u32 freq; + +/* + * Definition of register offsets + */ + +/* ID and Revision Register */ +#define ID_REV 0x0 + +/* Configuration Register */ +#define CFG 0x10 + +/* Interrupt Enable Register */ +#define INT_EN 0x14 +#define CH_INT_EN(c, i) ((1<event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction timer1_irq = { + .name = "Timer Tick", + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = timer1_interrupt, + .dev_id = &clockevent_atcpit100 +}; + +static void __init atcpit100_clockevent_init(int irq) +{ + struct clock_event_device *evt = &clockevent_atcpit100; + + evt->mult = div_sc(freq, NSEC_PER_SEC, evt->shift); + evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); + evt->min_delta_ns = clockevent_delta2ns(3, evt); + clockevents_register_device(evt); + setup_irq(irq, &timer1_irq); +} + +static int __init atcpit100_init(struct device_node *dev) +{ + int irq; + + base = of_iomap(dev, 0); + if (!base) { + pr_warn("Can't remap registers"); + return -ENXIO; + } + + if (of_property_read_u32(dev, "clock-frequency", &freq)) { + pr_warn("Can't read clock-frequency"); + return -EINVAL; + } + irq = irq_of_parse_and_map(dev, 0); + + if (irq <= 0) { + pr_warn("Failed to map timer IRQ\n"); + return -EINVAL; + } + pr_info("ATCPIT100 timer 1 installed on IRQ %d, with clock %d at %d HZ. in %p\n", + irq, freq, HZ, base); + writel(APB_CLK|TMR_32, base + CH_CTL(0)); + writel(readl(base + INT_EN) | CH_INT_EN(0, 0), base + INT_EN); + writel(readl(base + CH_EN) | CH_TMR_EN(0, 0), base + CH_EN); + atcpit100_clocksource_init(); + atcpit100_clockevent_init(irq); + + return 0; +} + +TIMER_OF_DECLARE(atcpit100, "andestech,atcpit100", atcpit100_init); -- 2.7.4