From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751511AbdKHH6c (ORCPT ); Wed, 8 Nov 2017 02:58:32 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:43758 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750951AbdKHH4t (ORCPT ); Wed, 8 Nov 2017 02:56:49 -0500 X-Google-Smtp-Source: ABhQp+QYmIBfhQjJ4lL2+reS82ta8LxKk3d+fyAtthGgJ/+mQ4BQ6bHYjwMZaqmoR7pYseMDq+icBA== From: Stephane Eranian To: linux-kernel@vger.kernel.org Cc: acme@redhat.com, peterz@infradead.org, mingo@elte.hu, ak@linux.intel.com, kan.liang@intel.com, jolsa@redhat.com Subject: [PATCH v3 2/5] perf/x86: add PERF_SAMPLE_SKID_IP support for X86 PEBS Date: Tue, 7 Nov 2017 23:56:34 -0800 Message-Id: <1510127797-22483-3-git-send-email-eranian@google.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510127797-22483-1-git-send-email-eranian@google.com> References: <1510127797-22483-1-git-send-email-eranian@google.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for SKID_IP for Intel x86 processors when PEBS mode is enabled. Signed-off-by: Stephane Eranian --- arch/x86/events/intel/ds.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 3674a4b6f8bd..52866a470b0d 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1190,6 +1190,13 @@ static void setup_pebs_sample_data(struct perf_event *event, x86_pmu.intel_cap.pebs_format >= 1) data->addr = pebs->dla; + /* + * unmodified, skid IP which is guaranteed to be the next + * dynamic instruction + */ + if (sample_type & PERF_SAMPLE_SKID_IP) + data->skid_ip = pebs->ip; + if (x86_pmu.intel_cap.pebs_format >= 2) { /* Only set the TSX weight when no memory weight. */ if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) -- 2.7.4