From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224O+QlG8qPuOWIrrKFNm5srkcncm39yC3QLhN1kF8Dl58EoKfLCN7O1x9JLHjjAg0OY5tAi ARC-Seal: i=1; a=rsa-sha256; t=1516476218; cv=none; d=google.com; s=arc-20160816; b=h3hQoOdE6IpE15e41a0Dly8219xTmJWFCOKasW0IIwNaUaqif5oxItNv60bXW/yTsa 03Nxp+Yxp4Cj5WpB/tHAVT1tjxeSDPzIM4w2G99lSxSNVMPxQM5n2IZblFl3GOEfHOiF 9qw9GiEz3OehIY6SHRQapZ4Rkz901eqjG5bQVCYI0Fbk54OyiKTLwwjLFN4t4pHbDNLY VfcEQWRJbrKvp5NCNhQGrMuwDu5Zi47KZbnQciU8nmP03LhMm0haVuTAMaFJO5w+60l7 87ziTVM+P9/J+Bm9wKnVBt4RfOcV+1+9saRLJMLvJwUpTItxnc1ObcAoTdlIQ4qo6xY8 d2mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=p5LGbqGcRUykA6/Num4OC6zgDrkwPFm9KiMgshKcl2k=; b=wsDbGY57tRGVm7mYAnv8UpA5GcBFGd4kFYSn5N7ZHHKQZg0PPM6Cx/PGgknVdY2Bgp N3bj59+FocjYst8FmObUeXXg3JRZfzRiabNZzFtZ1rnMUTSomebJeiwA2gEHTMtYDeCq zcuMhQejQjWBgP4z+TZ8j1fBNhsSQT6EuNLG663Smscp4RsPwkJITq0QOdImziMIDSR6 yXHnN+0RQAQKQQVTPdS8smo4ioxpuQqqRymeAk5lZYe9GXXVL23B4HqRJrC1rg7AR74A zX3XKaWArfcIMnPtvCdfzKMnvC3DSLd9gq/WfTPJXsS3MCmtOFIQ/TY6t0BYVegTGlSO Yt0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.de header.s=amazon201209 header.b=FZtgZYEn; spf=pass (google.com: domain of prvs=551b82ed1=karahmed@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=551b82ed1=karahmed@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.de Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.de header.s=amazon201209 header.b=FZtgZYEn; spf=pass (google.com: domain of prvs=551b82ed1=karahmed@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=551b82ed1=karahmed@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.de X-IronPort-AV: E=Sophos;i="5.46,387,1511827200"; d="scan'208";a="588403208" From: KarimAllah Ahmed To: linux-kernel@vger.kernel.org Cc: KarimAllah Ahmed , Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Arjan van de Ven , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , David Woodhouse , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Linus Torvalds , Masami Hiramatsu , Paolo Bonzini , Peter Zijlstra , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Thomas Gleixner , Tim Chen , Tom Lendacky , kvm@vger.kernel.org, x86@kernel.org Subject: [RFC 01/10] x86/speculation: Add basic support for IBPB Date: Sat, 20 Jan 2018 20:22:52 +0100 Message-Id: <1516476182-5153-2-git-send-email-karahmed@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516476182-5153-1-git-send-email-karahmed@amazon.de> References: <1516476182-5153-1-git-send-email-karahmed@amazon.de> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590140567332453729?= X-GMAIL-MSGID: =?utf-8?q?1590140567332453729?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Thomas Gleixner Expose indirect_branch_prediction_barrier() for use in subsequent patches. [karahmed: remove the special-casing of skylake for using IBPB (wtf?), switch to using ALTERNATIVES instead of static_cpu_has] [dwmw2: set up ax/cx/dx in the asm too so it gets NOP'd out] Signed-off-by: Thomas Gleixner Signed-off-by: KarimAllah Ahmed Signed-off-by: David Woodhouse --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/nospec-branch.h | 16 ++++++++++++++++ arch/x86/kernel/cpu/bugs.c | 7 +++++++ 3 files changed, 24 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 624d978..8ec9588 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -207,6 +207,7 @@ #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ +#define X86_FEATURE_IBPB ( 7*32+16) /* Using Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */ #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 4ad4108..c333c95 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -218,5 +218,21 @@ static inline void vmexit_fill_RSB(void) #endif } +static inline void indirect_branch_prediction_barrier(void) +{ + unsigned long ax, cx, dx; + + asm volatile(ALTERNATIVE("", + "movl %[msr], %%ecx\n\t" + "movl %[val], %%eax\n\t" + "movl $0, %%edx\n\t" + "wrmsr", + X86_FEATURE_IBPB) + : "=a" (ax), "=c" (cx), "=d" (dx) + : [msr] "i" (MSR_IA32_PRED_CMD), + [val] "i" (PRED_CMD_IBPB) + : "memory"); +} + #endif /* __ASSEMBLY__ */ #endif /* __NOSPEC_BRANCH_H__ */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 390b3dc..96548ff 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -249,6 +249,13 @@ static void __init spectre_v2_select_mitigation(void) setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); pr_info("Filling RSB on context switch\n"); } + + /* Initialize Indirect Branch Prediction Barrier if supported */ + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) || + boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) { + setup_force_cpu_cap(X86_FEATURE_IBPB); + pr_info("Enabling Indirect Branch Prediction Barrier\n"); + } } #undef pr_fmt -- 2.7.4