From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751100AbeAVLBZ (ORCPT ); Mon, 22 Jan 2018 06:01:25 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:35993 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750886AbeAVLBX (ORCPT ); Mon, 22 Jan 2018 06:01:23 -0500 X-Google-Smtp-Source: AH8x2254JRCPfgdd5kTdAzZFUW/uosNIGdOKu7GeSSGzq8TwBX9fel+vcjNHqhaY8meMCmMvyiBnyw== Message-ID: <1516618880.7870.1.camel@baylibre.com> Subject: Re: [PATCH] clk: meson: axg: fix the od shift of the sys_pll From: Jerome Brunet To: Yixun Lan , Neil Armstrong Cc: Michael Turquette , Stephen Boyd , Carlo Caione , Kevin Hilman , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 22 Jan 2018 12:01:20 +0100 In-Reply-To: <20180119020926.246887-1-yixun.lan@amlogic.com> References: <20180119020926.246887-1-yixun.lan@amlogic.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.4 (3.26.4-1.fc27) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2018-01-19 at 10:09 +0800, Yixun Lan wrote: > According to datasheet, the od shift of sys_pll is 16, > fix the typo which introduced at previous commit. > > Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers') > Signed-off-by: Yixun Lan > --- > drivers/clk/meson/axg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c > index 7988dc8506b0..04a231eaf648 100644 > --- a/drivers/clk/meson/axg.c > +++ b/drivers/clk/meson/axg.c > @@ -64,7 +64,7 @@ static struct meson_clk_pll axg_sys_pll = { > }, > .od = { > .reg_off = HHI_SYS_PLL_CNTL, > - .shift = 10, > + .shift = 16, > .width = 2, > }, > .lock = &meson_clk_lock, Looks good. Thx I'll take it when the rc1 is released Jerome