From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x225jHMuHWJYRej8UkkjaMbjb7nS0IEv5sm8w02GYmp1hsqr+VLy4TlvRhdJQ3LUoLPUSNt3v ARC-Seal: i=1; a=rsa-sha256; t=1516784557; cv=none; d=google.com; s=arc-20160816; b=R/I8yGaSH8Nu6JO3oR8UsSCt3pdudruxiS900qrQizbAbvrZ8hHXMrh8c/bb7HTzkQ djyW/lVuIb1v/UTbmhON+XCMAG/zyvnEWh3EJ12Opin68qbQcynvZTsvGqEuiLrK/Tn7 HKZGNWgI4QRFyxCvOOt+eCmWaBG86x4WgfwXMJ+TU0dRU26sWghfHKG49O9jrLPshNfs Oojj5V4U/LixaXTM65dNpwOXMB+pvP44Bf5/ulc2BCLiwFYOeGX1nAnUM5qkxby7N+o+ SpVO46DeeLxYcmBzCqi5AX51VLvrO5QPaKZZeAmLnPfWw1Xkp/KwteD2oTX+96kUzu/0 Y9pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:date:face:references:in-reply-to:cc:to:from:subject :message-id:dkim-signature:arc-authentication-results; bh=rWn1FrQvyWXBlbWqLsFuEyCliV1QWGl3Kewb0UPYg14=; b=O6NXVVJPd9s2SvFhDOMACG+O9DympeV6lguDO05gvhtKovNTpCiqooNPsf8p3AAeRK DGGg2wULK22lBpzLtf2sZcO8MMIkLjuaRM1NCdVji5l8rLKGKeqMxdmbJJHQRTXUl3Bt rMG6oBWy/Yqvnj1ODtkUia1m/ThojXkElqN4iuKbA7sMnnxaws0illPogvzxI2p65Nce 80e3ey4Phif4MhKtBzJbNg/5r2nw6VChYXCCqiDIg2stwuKloF/GX5GbfMjkO2aSn1VT r3N+s1Da9+Gbrblaa55t6eFRn5waMGH5dw7vgmILkKyCGn81Gr4aYeKmXajQKEbH8MYu sSOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@infradead.org header.s=twosheds.20170209 header.b=GjjjbJYK; spf=pass (google.com: best guess record for domain of batv+76e3c31b1e0c17bac38f+5267+infradead.org+dwmw2@twosheds.srs.infradead.org designates 2001:8b0:10b:1:21d:7dff:fe04:dbe2 as permitted sender) smtp.mailfrom=BATV+76e3c31b1e0c17bac38f+5267+infradead.org+dwmw2@twosheds.srs.infradead.org Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=twosheds.20170209 header.b=GjjjbJYK; spf=pass (google.com: best guess record for domain of batv+76e3c31b1e0c17bac38f+5267+infradead.org+dwmw2@twosheds.srs.infradead.org designates 2001:8b0:10b:1:21d:7dff:fe04:dbe2 as permitted sender) smtp.mailfrom=BATV+76e3c31b1e0c17bac38f+5267+infradead.org+dwmw2@twosheds.srs.infradead.org Message-ID: <1516784541.13558.90.camel@infradead.org> Subject: Re: [RFC 05/10] x86/speculation: Add basic IBRS support infrastructure From: David Woodhouse To: Peter Zijlstra Cc: Thomas Gleixner , KarimAllah Ahmed , linux-kernel@vger.kernel.org, Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Arjan van de Ven , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Linus Torvalds , Masami Hiramatsu , Paolo Bonzini , Radim =?UTF-8?Q?Kr=C4=8Dm=C3=A1=C5=99?= , Tim Chen , Tom Lendacky , kvm@vger.kernel.org, x86@kernel.org In-Reply-To: <20180124084735.GM2228@hirez.programming.kicks-ass.net> References: <1516476182-5153-1-git-send-email-karahmed@amazon.de> <1516476182-5153-6-git-send-email-karahmed@amazon.de> <1516741116.13558.11.camel@infradead.org> <20180124084735.GM2228@hirez.programming.kicks-ass.net> Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAG1BMVEUHBwcUFBQpKSlGRkZhYWF9fX2Xl5eysrLMzMxFF+rXAAACaElEQVQ4y21UQXbbIBQE9wJALmAg6ToWON22FrhZthHgbvssUPathC7QWMful2JHSmtWwGg+zPxBCE0DU4QoJQgRgsg4w2gJjBNE8PjFBZgnQMBs+uZ1NQNQjZO3BV4AGDFC0f+l4DBG0VUAM4yv7SO8IgRdHXQ+A78HKL5OAeCfNQV5cHX8DsBUyIJKtYbt98BKaGNCKjfgFVkqYVLbkHKsRsbSCSa0T6npIqLrpRBgQKHUpQmgs9eEKaiUcooE8WWfCGVnBiUcn1uF2XhbfmN9apKnmMP2K4kizKkQWxuaVNOpU2cACIyxO1Po8ETHcXEDMVnozcejkAYA9iaD4pU0ZvNQ8VurNnTuFAYVtuIPUZW25PjDIjQAlGyffIiRQxoWAZBmJ0LTdW2Nyc0iP3DqRhxizvGJkBWZmyFVyZkddWzmBoIBVMpCCJ1CFzl98xav4VJKSSD45KbUT75ixikTphDSRh8+Uz7JLgUTAgAFwzqzjxc/nDY7WUApqY0OMdTwCKZSXplSKkgIRCHElCp8ZnhnKqXuwcNbk1L0VXE+I9alUXoHlLHl3mv7/dWQlJwtjREC7mu9L/U2jQyMUuO2EDS4q9Kl2ddm232bxIE5pjJuVwiljNn/Cfv25/T0cu5cZbwHGVq7h/zp0B4n3S99V/utD+Uo8BiGx9xCsOAV5z7/tjo4Z4z1Lvb90KZ7eFOoOeXOukqF2seo234YYuaQPpRP+cVZU5adT1Edun5Iz3z8fTz3+eSDh0Ip1c7zx1MaijGzTd/3MbRuBHz8cvcVgCMBRpOHvgu59WDhoat+nIZm+LWm9C/aaaGq5DCP9QAAAABJRU5ErkJggg== Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-oGndH9L9+zjA+3If/9ts" Date: Wed, 24 Jan 2018 09:02:21 +0000 Mime-Version: 1.0 X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 X-SRS-Rewrite: SMTP reverse-path rewritten from by twosheds.infradead.org. See http://www.infradead.org/rpr.html X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590140581449802182?= X-GMAIL-MSGID: =?utf-8?q?1590463884516566411?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: --=-oGndH9L9+zjA+3If/9ts Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2018-01-24 at 09:47 +0100, Peter Zijlstra wrote: > Typically tglx likes to use x86_match_cpu() for these things; see also > commit: bd9240a18edfb ("x86/apic: Add TSC_DEADLINE quirk due to > errata"). Thanks, will fix. I think we might also end up in whitelist mode, adding "known good" microcodes to the list as they get released or retroactively blessed. I would really have liked a new bit in IA32_ARCH_CAPABILITIES to say that it's safe, but that's not possible for *existing* microcode which actually turns out to be OK in the end. That means the whitelist ends up basically empty right now. Should I add a command line parameter to override it? Otherwise we end up having to rebuild the kernel every time there's a microcode release which covers a new CPU SKU (which is why I kind of hate the whitelist, but Arjan is very insistent...) I'm kind of tempted to turn it into a whitelist just by adding 1 to the microcode revision in each table entry. Sure, that N+1 might be another microcode build that also has issues but never saw the light of day... but that's OK as long it never *does*. And yes we'd have to tweak it if revisions that are blacklisted in the Intel doc are subsequently cleared. But at least it'd require *less* tweaking. > >=20 > > + > > +static int bad_spectre_microcode(struct cpuinfo_x86 *c) > > +{ > > + int i; > > + > > + for (i =3D 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { > > + if (c->x86_model =3D=3D spectre_bad_microcodes[i].model && > > + =C2=A0=C2=A0=C2=A0=C2=A0c->x86_mask =3D=3D spectre_bad_microcodes[i]= .stepping) > > + return (c->microcode <=3D spectre_bad_microcodes[i].microcode); > > + } > > + return 0; > > +} > The above is Intel only, you should check vendor too I think. It's in intel.c, called from early_init_intel(). Isn't that sufficient? > >=20 > > =C2=A0static void early_init_intel(struct cpuinfo_x86 *c) > > =C2=A0{ > > =C2=A0 u64 misc_enable; > > @@ -122,6 +173,18 @@ static void early_init_intel(struct cpuinfo_x86 *c= ) > > =C2=A0 if (c->x86 >=3D 6 && !cpu_has(c, X86_FEATURE_IA64)) > > =C2=A0 c->microcode =3D intel_get_microcode_revision(); > > =C2=A0 > > + if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cpu_has(c, X86_FEATURE_AMD_SPEC_CTRL) |= | > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cpu_has(c, X86_FEATURE_AMD_PRED_CMD) || > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cpu_has(c, X86_FEATURE_AMD_STIBP)) && b= ad_spectre_microcode(c)) { > > + pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_= CTRL\n"); > > + clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL); > > + clear_cpu_cap(c, X86_FEATURE_STIBP); > > + clear_cpu_cap(c, X86_FEATURE_AMD_SPEC_CTRL); > > + clear_cpu_cap(c, X86_FEATURE_AMD_PRED_CMD); > > + clear_cpu_cap(c, X86_FEATURE_AMD_STIBP); > > + } > And since its Intel only, what are those AMD features doing there? Hypervisors which only want to expose PRED_CMD may do so using the AMD feature bit. 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