Re: [PATCH 12/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

Sricharan R
2018-02-07T04:01:05Z

Hi Abhishek,

<snip ..>

>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2017, The Linux Foundation. All rights reserved.
>> +
>> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
>> +
>> +/ {
>> +    model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C2";
>
>  s/IPQ40xx/IPQ4019
>
ok

>> +
>> +    soc {
>> +        pcie0: pci@40000000 {
>> +            status = "disabled";
>> +        };
>
>  We can disable in base dtsi itself.
>

hmm, as mentioned in the previous patch, feels better to enable
it only in the board file specifically and not to touch this here
and the common dtsi.

>> +
>> +        pinctrl@1000000 {
>> +            serial_1_pins: serial1_pinmux {
>> +                mux {
>> +                    pins = "gpio8", "gpio9";
>> +                    function = "blsp_uart1";
>> +                    bias-disable;
>> +                };
>> +            };
>> +
>> +            spi_0_pins: spi_0_pinmux {
>> +                mux {
>> +                    pins = "gpio13", "gpio14",
>> "gpio15";
>> +                    function = "blsp_spi0";
>> +                    bias-disable;
>> +                };
>> +                cs1 {
>> +                    pins = "gpio12";
>> +                    function = "gpio";
>> +                };
>> +                host_int1 {
>> +                    pins = "gpio10";
>> +                    function = "gpio";
>> +                    input;
>> +                };
>> +                cs2 {
>> +                    pins = "gpio45";
>> +                    function = "gpio";
>> +                };
>> +                host_int2 {
>> +                    pins = "gpio61";
>> +                    function = "gpio";
>> +                    input;
>> +                };
>> +                rst {
>> +                    pins = "gpio36";
>> +                    function = "gpio";
>> +                    output-high;
>> +                };
>
>  Normally spi pins should contains spi protocol related pins
>  could you please explain what is the role of host_pin and rst
>  pins and which driver will use these.
>

hmm, the additional pins were required for zigbee connected as the
spidev device. So the right probably is to have the additional
pins required for the device populated under the spi's child node.

>> +            };
>> +        };
>> +
>> +        serial@78b0000 {
>> +            pinctrl-0 = <&serial_1_pins>;
>> +            pinctrl-names = "default";
>> +            status = "ok";
>> +        };
>> +
>> +        spi_0: spi@78b5000 { /* BLSP1 QUP1 */
>> +            pinctrl-0 = <&spi_0_pins>;
>> +            pinctrl-names = "default";
>> +            status = "ok";
>
>  From pinmux, it looks like multiple gpio based cs are being
>  used so do we need to specify cs-gpios like dk01-c2.
>

ok, let me check.

Regards,
Sricharan

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