From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934174AbeCHOb5 (ORCPT ); Thu, 8 Mar 2018 09:31:57 -0500 Received: from mail-he1eur01on0117.outbound.protection.outlook.com ([104.47.0.117]:45370 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755559AbeCHOba (ORCPT ); Thu, 8 Mar 2018 09:31:30 -0500 From: Marcel Ziswiler To: "thierry.reding@gmail.com" CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "jonathanh@nvidia.com" , "linux@armlinux.org.uk" , "devicetree@vger.kernel.org" , "digetx@gmail.com" , "mark.rutland@arm.com" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" Subject: Re: [PATCH v2] ARM: tegra: fix ulpi regression on tegra20 Thread-Topic: [PATCH v2] ARM: tegra: fix ulpi regression on tegra20 Thread-Index: AQHTq+rZh4FxrXNPTEqh+gv+36lx2aPGd9uAgAAElYA= Date: Thu, 8 Mar 2018 14:31:26 +0000 Message-ID: <1520519485.23006.6.camel@toradex.com> References: <20180222143825.1517-1-marcel@ziswiler.com> <20180308141501.GH3529@ulmo> In-Reply-To: <20180308141501.GH3529@ulmo> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=marcel.ziswiler@toradex.com; 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charset="utf-8" Content-ID: <5172D0DCC432A84FB5D47AB81AFAED9A@eurprd05.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: toradex.com X-MS-Exchange-CrossTenant-Network-Message-Id: 351797a3-d152-49d3-1af0-08d5850146b5 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Mar 2018 14:31:26.9122 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d9995866-0d9b-4251-8315-093f062abab4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR05MB1426 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w28EW2oD024864 On Thu, 2018-03-08 at 15:15 +0100, Thierry Reding wrote: > On Thu, Feb 22, 2018 at 03:38:25PM +0100, Marcel Ziswiler wrote: > > From: Marcel Ziswiler > > > > Since commit f8f8f1d04494 ("clk: Don't touch hardware when > > reparenting > > during registration") ULPI has been broken on Tegra20 leading to > > the > > following error message during boot: > > > > [ 1.974698] ulpi_phy_power_on: ulpi write failed > > [ 1.979384] tegra-ehci c5004000.usb: Failed to power on the phy > > [ 1.985434] tegra-ehci: probe of c5004000.usb failed with error > > -110 > > > > Debugging through the changes and finally also consulting the TRM > > revealed that rather than the CDEV2 clock off OSC requiring such > > pin > > muxing actually the PLL_P_OUT4 clock is in use. It looks like so > > far it > > just worked by chance of that one having been enabled which > > Stephen's > > commit now changed when reparenting sclk away from pll_p_out4 > > leaving > > that one disabled. Fix this by properly assigning the PLL_P_OUT4 > > clock > > as the ULPI PHY clock. > > > > Signed-off-by: Marcel Ziswiler > > > > --- > > > > Changes in v2: > > - Updated device tree binding documentation as well. > > - CCing Dmitry as well. > > > > Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt | > > 4 +++- > > arch/arm/boot/dts/tegra20.dtsi | > > 2 +- > > 2 files changed, 4 insertions(+), 2 deletions(-) > > Applied, though I've split this into two separate patches, one going > into for-4.17/dt-bindings and the other going into for-4.17/arm/dt. Thanks, Thierry! BTW: Do you know what is happening with my T30 USB patch? Is there anything I may do about it? > Thanks, > Thierry