From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423154AbcFHUkg (ORCPT ); Wed, 8 Jun 2016 16:40:36 -0400 Received: from gloria.sntech.de ([95.129.55.99]:59309 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932233AbcFHUke (ORCPT ); Wed, 8 Jun 2016 16:40:34 -0400 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Rob Herring Cc: Shawn Lin , Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Doug Anderson , Wenrui Li , devicetree@vger.kernel.org Subject: Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Date: Wed, 08 Jun 2016 22:40:19 +0200 Message-ID: <1524911.R4OXTTYFIK@diego> User-Agent: KMail/4.14.10 (Linux/4.4.0-1-amd64; KDE/4.14.14; x86_64; ; ) In-Reply-To: <20160608202900.GA25662@rob-hp-laptop> References: <1465370708-23619-1-git-send-email-shawn.lin@rock-chips.com> <20160608202900.GA25662@rob-hp-laptop> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Mittwoch, 8. Juni 2016, 15:29:00 schrieb Rob Herring: > gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote: > > This patch adds a binding that describes the Rockchip PCIe PHY > > found on Rockchip SoCs PCIe interface. > > > > Signed-off-by: Shawn Lin > > --- > > > > .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 > > ++++++++++++++++++++++ 1 file changed, 22 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt> > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt > > b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file > > mode 100644 > > index 0000000..ba8c406 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt > > @@ -0,0 +1,22 @@ > > +Rockchip PCIE PHY > > +----------------------- > > + > > +Required properties: > > + - compatible: rockchip,rk3399-pcie-phy > > + - #phy-cells: must be 0 > > + > > +Example: > > + > > +grf: syscon@ff770000 { > > + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + ... > > + > > + pcie_phy: phy@e220 { > > unit-address needs a reg property or drop the unit address. I'd do the > former if there's a register range you can describe here. Hmm, I think I'd suggest going the other way - call the node pcie-phy . While the General Register Files do contain some specific address ranges (like for the emmc phy, or some performance monitor things), the register at 0xe220 is a shared register (GRF_SOC_CON8), containing both i2s and pcie setting bits. Specifying register ranges suggests some form of exclusivity to me - which is just great for things like the emmc phy that has an actual range, but for a device being controlled from some shared register. Heiko