From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Andy Lutomirski <luto@kernel.org>,
"H . Peter Anvin" <hpa@zytor.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@kernel.org>
Cc: Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Markus T Metzger <markus.t.metzger@intel.com>,
Ravi Shankar <ravi.v.shankar@intel.com>,
"Chang S . Bae" <chang.seok.bae@intel.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH v4 2/7] x86/fsgsbase/64: Make ptrace read FS/GS base accurately
Date: Wed, 20 Jun 2018 16:15:01 -0700 [thread overview]
Message-ID: <1529536506-26237-3-git-send-email-chang.seok.bae@intel.com> (raw)
In-Reply-To: <1529536506-26237-1-git-send-email-chang.seok.bae@intel.com>
From: Andy Lutomirski <luto@kernel.org>
ptrace can read FS/GS base using the register access API
(PTRACE_PEEKUSER, etc) or PTRACE_ARCH_PRCTL. Make both of these
mechanisms return the actual FS/GS base.
This will improve debuggability by providing the correct information
to ptracer (GDB and etc).
Signed-off-by: Andy Lutomirski <luto@kernel.org>
[chang: Rebase and revise patch description]
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/process_64.c | 67 +++++++++++++++++++++++++++++++++-----------
1 file changed, 51 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index ace0158..e498671 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -279,6 +279,49 @@ static __always_inline void load_seg_legacy(unsigned short prev_index,
}
}
+static unsigned long task_seg_base(struct task_struct *task,
+ unsigned short selector)
+{
+ unsigned short idx = selector >> 3;
+ unsigned long base;
+
+ if (likely((selector & SEGMENT_TI_MASK) == 0)) {
+ if (unlikely(idx >= GDT_ENTRIES))
+ return 0;
+
+ /*
+ * There are no user segments in the GDT with nonzero bases
+ * other than the TLS segments.
+ */
+ if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
+ return 0;
+
+ idx -= GDT_ENTRY_TLS_MIN;
+ base = get_desc_base(&task->thread.tls_array[idx]);
+ } else {
+#ifdef CONFIG_MODIFY_LDT_SYSCALL
+ struct ldt_struct *ldt;
+
+ /*
+ * If performance here mattered, we could protect the LDT
+ * with RCU. This is a slow path, though, so we can just
+ * take the mutex.
+ */
+ mutex_lock(&task->mm->context.lock);
+ ldt = task->mm->context.ldt;
+ if (unlikely(idx >= ldt->nr_entries))
+ base = 0;
+ else
+ base = get_desc_base(ldt->entries + idx);
+ mutex_unlock(&task->mm->context.lock);
+#else
+ base = 0;
+#endif
+ }
+
+ return base;
+}
+
void write_fsbase(unsigned long fsbase)
{
/* set the selector to 0 to not confuse __switch_to */
@@ -297,16 +340,12 @@ unsigned long read_task_fsbase(struct task_struct *task)
{
unsigned long fsbase;
- if (task == current) {
+ if (task == current)
fsbase = read_fsbase();
- } else {
- /*
- * XXX: This will not behave as expected if called
- * if fsindex != 0. This preserves an existing bug
- * that will be fixed.
- */
+ else if (task->thread.fsindex == 0)
fsbase = task->thread.fsbase;
- }
+ else
+ fsbase = task_seg_base(task, task->thread.fsindex);
return fsbase;
}
@@ -315,16 +354,12 @@ unsigned long read_task_gsbase(struct task_struct *task)
{
unsigned long gsbase;
- if (task == current) {
+ if (task == current)
gsbase = read_inactive_gsbase();
- } else {
- /*
- * XXX: This will not behave as expected if called
- * if gsindex != 0. Same bug preservation as above
- * read_task_fsbase.
- */
+ else if (task->thread.gsindex == 0)
gsbase = task->thread.gsbase;
- }
+ else
+ gsbase = task_seg_base(task, task->thread.gsindex);
return gsbase;
}
--
2.7.4
next prev parent reply other threads:[~2018-06-20 23:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-20 23:14 [PATCH v4 0/7] x86: infrastructure to enable FSGSBASE Chang S. Bae
2018-06-20 23:15 ` [PATCH v4 1/7] x86/fsgsbase/64: Introduce FS/GS base helper functions Chang S. Bae
2018-06-22 14:28 ` Thomas Gleixner
2018-06-22 14:50 ` Andy Lutomirski
2018-06-22 15:39 ` Thomas Gleixner
2018-06-22 16:08 ` Andy Lutomirski
2018-06-22 18:09 ` Bae, Chang Seok
2018-06-20 23:15 ` Chang S. Bae [this message]
2018-06-22 14:37 ` [PATCH v4 2/7] x86/fsgsbase/64: Make ptrace read FS/GS base accurately Thomas Gleixner
2018-06-20 23:15 ` [PATCH v4 3/7] x86/fsgsbase/64: Use FS/GS base helpers in core dump Chang S. Bae
2018-06-22 14:43 ` Thomas Gleixner
2018-06-20 23:15 ` [PATCH v4 4/7] x86/fsgsbase/64: Factor out load FS/GS segments from __switch_to Chang S. Bae
2018-06-22 14:32 ` Thomas Gleixner
2018-06-20 23:15 ` [PATCH v4 5/7] x86/segments/64: Rename PER_CPU segment to CPU_NUMBER Chang S. Bae
2018-06-22 14:32 ` Thomas Gleixner
2018-06-20 23:15 ` [PATCH v4 6/7] x86/vdso: Introduce CPU number helper functions Chang S. Bae
2018-06-22 15:14 ` Thomas Gleixner
2018-06-22 18:46 ` Bae, Chang Seok
2018-06-22 19:07 ` Thomas Gleixner
2018-06-20 23:15 ` [PATCH v4 7/7] x86/vdso: Move out the CPU number store Chang S. Bae
2018-06-22 15:18 ` Thomas Gleixner
2018-06-22 16:11 ` Andy Lutomirski
2018-06-22 16:18 ` Thomas Gleixner
2018-06-22 18:02 ` Bae, Chang Seok
2018-06-22 22:02 ` Andy Lutomirski
2018-06-25 15:40 ` Thomas Gleixner
2018-06-25 18:00 ` H. Peter Anvin
2018-06-25 19:40 ` Thomas Gleixner
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