From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58A1FC43142 for ; Mon, 25 Jun 2018 07:10:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12B3A25504 for ; Mon, 25 Jun 2018 07:10:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 12B3A25504 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752425AbeFYHKL (ORCPT ); Mon, 25 Jun 2018 03:10:11 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:11306 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751066AbeFYHKJ (ORCPT ); Mon, 25 Jun 2018 03:10:09 -0400 X-UUID: d33da671234f415eba1a401905261b20-20180625 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 566745337; Mon, 25 Jun 2018 15:10:06 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 25 Jun 2018 15:10:03 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 25 Jun 2018 15:10:03 +0800 From: Stanley Chu To: Matthias Brugger , Daniel Lezcano , Thomas Gleixner , Rob Herring CC: , , , , Stanley Chu Subject: [PATCH 1/2] dt-bindings: Add mtk-systimer bindings Date: Mon, 25 Jun 2018 15:10:00 +0800 Message-ID: <1529910601-15005-2-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1529910601-15005-1-git-send-email-stanley.chu@mediatek.com> References: <1529910601-15005-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding documentation for the System Timer driver of the Mediatek SoCs. Signed-off-by: Stanley Chu --- .../bindings/timer/mediatek,mtk-systimer.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/mediatek,mtk-systimer.txt diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-systimer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-systimer.txt new file mode 100644 index 0000000..735a6fd --- /dev/null +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-systimer.txt @@ -0,0 +1,18 @@ +Mediatek System Timers +---------------------- + +Required properties: +- compatible: should contain + "mediatek,sys_timer" for those platforms which support system timer. +- reg: Mandatory. The location and length for system timer registers. +- clock-frequency: Optional. If not assigned specifically, default + value 13000000 (means 13 MHz) would be applied. + +Examples: + + sys_timer@10017000 { + compatible = "mediatek,sys_timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clock-frequency = <13000000>; + }; -- 1.7.9.5