From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E761EC43144 for ; Thu, 28 Jun 2018 10:47:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A80E42725A for ; Thu, 28 Jun 2018 10:47:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A80E42725A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934031AbeF1KrR (ORCPT ); Thu, 28 Jun 2018 06:47:17 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:14662 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S933822AbeF1Kpx (ORCPT ); Thu, 28 Jun 2018 06:45:53 -0400 X-UUID: 1c8abf6397ea42958e09ea0dd343c68a-20180628 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1355699886; Thu, 28 Jun 2018 18:45:49 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 28 Jun 2018 18:45:47 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 28 Jun 2018 18:45:47 +0800 From: Stanley Chu To: Matthias Brugger , Daniel Lezcano , Thomas Gleixner , Rob Herring CC: , , , , Stanley Chu Subject: [PATCH v3 1/5] clocksource/drivers/timer-mediatek: Add system timer bindings Date: Thu, 28 Jun 2018 18:45:40 +0800 Message-ID: <1530182744-10731-2-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1530182744-10731-1-git-send-email-stanley.chu@mediatek.com> References: <1530182744-10731-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixes bindings of existed "General Purpose Timer", and then add bindings of new "System Timer" on Mediatek SoCs. Signed-off-by: Stanley Chu --- .../bindings/timer/mediatek,mtk-timer.txt | 38 ++++++++++++++++---- 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index b1fe7e9..d42247b 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -1,5 +1,14 @@ -Mediatek MT6577, MT6572 and MT6589 Timers ---------------------------------------- +Mediatek Timers +--------------- + +Mediatek SoCs have two different timers on different platforms, +- GPT (General Purpose Timer) +- SYST (System Timer) + +Please bind correct timers in each platforms. + + +** General Purpose Timer (GPT) Required properties: - compatible should contain: @@ -11,9 +20,8 @@ Required properties: * "mediatek,mt8135-timer" for MT8135 compatible timers * "mediatek,mt8173-timer" for MT8173 compatible timers * "mediatek,mt6577-timer" for MT6577 and all above compatible timers -- reg: Should contain location and length for timers register. -- clocks: Clocks driving the timer hardware. This list should include two - clocks. The order is system clock and as second clock the RTC clock. +- reg: Should contain location and length for GPT register. +- clocks: GPT is drived by system clock. Examples: @@ -21,5 +29,23 @@ Examples: compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; + clocks = <&system_clk>; + }; + + +** System Timer (SYST) + +Required properties: +- compatible: Should contain + * "mediatek,mt6765-systimer" for MT6765 compatible timers +- reg: Should contain the location and length for system timer registers. +- clocks: System timer is drived by system clock. + +Examples: + + systimer@10017000 { + compatible = "mediatek,mt6765-systimer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&system_clk>; }; -- 1.7.9.5