From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B286C433F5 for ; Wed, 5 Sep 2018 10:47:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 27E4620658 for ; Wed, 5 Sep 2018 10:47:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 27E4620658 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727762AbeIEPRE (ORCPT ); Wed, 5 Sep 2018 11:17:04 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:60830 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726035AbeIEPRD (ORCPT ); Wed, 5 Sep 2018 11:17:03 -0400 X-UUID: 36d9d93a93c840dab043e0cbaba552ea-20180905 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 908757454; Wed, 05 Sep 2018 18:47:16 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 5 Sep 2018 18:47:15 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 5 Sep 2018 18:47:14 +0800 Message-ID: <1536144434.4618.1.camel@mtksdaap41> Subject: Re: [PATCH v2 03/13] drm/mediatek: adjust EDGE to match clock and data From: CK Hu To: Bibby Hsieh CC: David Airlie , Matthias Brugger , Daniel Vetter , , , Yingjoe Chen , Cawa Cheng , Daniel Kurtz , "Philipp Zabel" , YT Shen , "Thierry Reding" , Mao Huang , , , "Sascha Hauer" , chunhui dai Date: Wed, 5 Sep 2018 18:47:14 +0800 In-Reply-To: <20180905083146.14727-4-bibby.hsieh@mediatek.com> References: <20180905083146.14727-1-bibby.hsieh@mediatek.com> <20180905083146.14727-4-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bibby: On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote: > From: chunhui dai > > The default timing of DPI data and clock is not match. > We could adjust this bit to make them match. > > Signed-off-by: chunhui dai Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++++++++ > drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 3db959fed493..df27107b1f0b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { > > struct mtk_dpi_conf { > const u32 reg_h_fre_con; > + bool edge_sel_en; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) > @@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) > mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); > } > > +static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) > +{ > + if (dpi->conf->edge_sel_en) > + mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); > +} > + > static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, > enum mtk_dpi_out_color_format format) > { > @@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > mtk_dpi_config_yc_map(dpi, dpi->yc_map); > mtk_dpi_config_color_format(dpi, dpi->color_format); > mtk_dpi_config_2n_h_fre(dpi); > + mtk_dpi_config_disable_edge(dpi); > mtk_dpi_sw_reset(dpi, false); > > return 0; > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h > index 040444d7718d..d9db8c4cacd7 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h > +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h > @@ -223,5 +223,6 @@ > #define ESAV_CODE2 (0xFFF << 0) > #define ESAV_CODE3_MSB BIT(16) > > +#define EDGE_SEL_EN BIT(5) > #define H_FRE_2N BIT(25) > #endif /* __MTK_DPI_REGS_H */