From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77861ECDE2B for ; Mon, 8 Oct 2018 03:25:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4587020882 for ; Mon, 8 Oct 2018 03:25:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4587020882 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726984AbeJHKes (ORCPT ); Mon, 8 Oct 2018 06:34:48 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:51367 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726096AbeJHKeq (ORCPT ); Mon, 8 Oct 2018 06:34:46 -0400 X-UUID: cfbfdb52f32a45769458be1293c0586d-20181008 X-UUID: cfbfdb52f32a45769458be1293c0586d-20181008 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 348596383; Mon, 08 Oct 2018 11:25:05 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 8 Oct 2018 11:25:04 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 8 Oct 2018 11:25:03 +0800 From: To: , , , , , , CC: , , , , , , , , , Subject: [PATCH v6 6/9] PCI: mediatek: Fixup enable msi logic by enable msi after clock enabled Date: Mon, 8 Oct 2018 11:24:45 +0800 Message-ID: <1538969088-7136-7-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com> References: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 27C4FDAA8AFF7CAFDB39BEAF31B8E2F43DCC232D8DEB571A7C2EA7A6D481EC6F2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Honghui Zhang The commit 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622") added MSI support but enable MSI in wrong place, clocks was not enabled when enable MSI. This patch fix this issue by calling mtk_pcie_enable_msi in mtk_pcie_startup_port_v2 since the clock was all enabled at that time. Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/controller/pcie-mediatek.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 654a63e..d3f4694 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -568,8 +568,6 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, ret = mtk_pcie_allocate_msi_domains(port); if (ret) return ret; - - mtk_pcie_enable_msi(port); } return 0; @@ -690,6 +688,9 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val &= ~INTX_MASK; writel(val, port->base + PCIE_INT_MASK); + if (IS_ENABLED(CONFIG_PCI_MSI)) + mtk_pcie_enable_msi(port); + /* Set AHB to PCIe translation windows */ size = mem->end - mem->start; val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size)); -- 2.6.4